/*
 *******************************************************************************
 *
 * Copyright (c) 2017 Advanced Micro Devices, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 ******************************************************************************/

#pragma once

#define cfgnbif_gpuADAPTER_ID_W_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuADAPTER_ID_epf_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuBASE_ADDR_1_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBASE_ADDR_1_epvf_DEFAULT             0x0000
#define cfgnbif_gpuBASE_ADDR_1_swds_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuBASE_ADDR_2_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBASE_ADDR_2_epvf_DEFAULT             0x0000
#define cfgnbif_gpuBASE_ADDR_3_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBASE_ADDR_3_epvf_DEFAULT             0x0000
#define cfgnbif_gpuBASE_ADDR_4_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBASE_ADDR_4_epvf_DEFAULT             0x0000
#define cfgnbif_gpuBASE_ADDR_5_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBASE_ADDR_5_epvf_DEFAULT             0x0000
#define cfgnbif_gpuBASE_ADDR_6_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBASE_ADDR_6_epvf_DEFAULT             0x0000
#define cfgnbif_gpuBASE_CLASS_epf_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuBASE_CLASS_epvf_DEFAULT              0x0000
#define cfgnbif_gpuBASE_CLASS_swds_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuBIST_epf_DEFAULT__GFX09              0x0000
#define cfgnbif_gpuBIST_epvf_DEFAULT                    0x0000
#define cfgnbif_gpuBIST_swds_DEFAULT__GFX09             0x0000
#define cfgnbif_gpuCACHE_LINE_epf_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuCACHE_LINE_epvf_DEFAULT              0x0000
#define cfgnbif_gpuCACHE_LINE_swds_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuCAP_PTR_epf_DEFAULT__GFX09           0x0000
#define cfgnbif_gpuCAP_PTR_swds_DEFAULT__GFX09          0x0050
#define cfgnbif_gpuCOMMAND_epf_DEFAULT__GFX09           0x0000
#define cfgnbif_gpuCOMMAND_epvf_DEFAULT                 0x0000
#define cfgnbif_gpuCOMMAND_swds_DEFAULT__GFX09          0x0000
#define cfgnbif_gpuDEVICE_CAP2_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuDEVICE_CAP2_epvf_DEFAULT             0x0000
#define cfgnbif_gpuDEVICE_CAP2_swds_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuDEVICE_CAP_epf_DEFAULT__GFX09        0x10000020
#define cfgnbif_gpuDEVICE_CAP_swds_DEFAULT__GFX09       0x0020
#define cfgnbif_gpuDEVICE_CNTL2_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuDEVICE_CNTL2_epvf_DEFAULT            0x0000
#define cfgnbif_gpuDEVICE_CNTL2_swds_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuDEVICE_CNTL_epf_DEFAULT__GFX09       0x2810
#define cfgnbif_gpuDEVICE_CNTL_epvf_DEFAULT             0x0000
#define cfgnbif_gpuDEVICE_CNTL_swds_DEFAULT__GFX09      0x2810
#define cfgnbif_gpuDEVICE_ID_epf_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuDEVICE_ID_epvf_DEFAULT               0xFFFF
#define cfgnbif_gpuDEVICE_ID_swds_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuDEVICE_STATUS2_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuDEVICE_STATUS2_epvf_DEFAULT          0x0000
#define cfgnbif_gpuDEVICE_STATUS2_swds_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuDEVICE_STATUS_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuDEVICE_STATUS_epvf_DEFAULT           0x0000
#define cfgnbif_gpuDEVICE_STATUS_swds_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuHEADER_epf_DEFAULT__GFX09            0x0000
#define cfgnbif_gpuHEADER_epvf_DEFAULT                  0x0000
#define cfgnbif_gpuHEADER_swds_DEFAULT__GFX09           0x0001
#define cfgnbif_gpuINTERRUPT_LINE_epf_DEFAULT__GFX09    0x00FF
#define cfgnbif_gpuINTERRUPT_LINE_epvf_DEFAULT          0x0000
#define cfgnbif_gpuINTERRUPT_LINE_swds_DEFAULT__GFX09   0x00FF
#define cfgnbif_gpuINTERRUPT_PIN_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuINTERRUPT_PIN_epvf_DEFAULT           0x0000
#define cfgnbif_gpuINTERRUPT_PIN_swds_DEFAULT__GFX09    0x0001
#define cfgnbif_gpuIO_BASE_LIMIT_HI_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuIO_BASE_LIMIT_swds_DEFAULT__GFX09    0x0101
#define cfgnbif_gpuIRQ_BRIDGE_CNTL_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuLATENCY_epf_DEFAULT__GFX09           0x0000
#define cfgnbif_gpuLATENCY_epvf_DEFAULT                 0x0000
#define cfgnbif_gpuLATENCY_swds_DEFAULT__GFX09          0x0000
#define cfgnbif_gpuLINK_CAP2_epf_DEFAULT__GFX09         0x000E
#define cfgnbif_gpuLINK_CAP2_epvf_DEFAULT               0x000E
#define cfgnbif_gpuLINK_CAP2_swds_DEFAULT__GFX09        0x000E
#define cfgnbif_gpuLINK_CAP_epf_DEFAULT__GFX09          0x411C03
#define cfgnbif_gpuLINK_CAP_swds_DEFAULT__GFX09         0x411C03
#define cfgnbif_gpuLINK_CNTL2_epf_DEFAULT__GFX09        0x0003
#define cfgnbif_gpuLINK_CNTL2_epvf_DEFAULT              0x0000
#define cfgnbif_gpuLINK_CNTL2_swds_DEFAULT__GFX09       0x0003
#define cfgnbif_gpuLINK_CNTL_epf_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuLINK_CNTL_epvf_DEFAULT               0x0000
#define cfgnbif_gpuLINK_CNTL_swds_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuLINK_STATUS2_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuLINK_STATUS2_epvf_DEFAULT            0x0000
#define cfgnbif_gpuLINK_STATUS2_swds_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuLINK_STATUS_epf_DEFAULT__GFX09       0x1001
#define cfgnbif_gpuLINK_STATUS_epvf_DEFAULT             0x0000
#define cfgnbif_gpuLINK_STATUS_swds_DEFAULT__GFX09      0x3001
#define cfgnbif_gpuMAX_LATENCY_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuMEM_BASE_LIMIT_swds_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuMIN_GRANT_epf_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuMSIX_CAP_LIST_epf_DEFAULT__GFX09     0x0011
#define cfgnbif_gpuMSIX_CAP_LIST_epvf_DEFAULT           0x0011
#define cfgnbif_gpuMSIX_MSG_CNTL_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuMSIX_MSG_CNTL_epvf_DEFAULT           0x0000
#define cfgnbif_gpuMSIX_PBA_epf_DEFAULT__GFX09          0x0000
#define cfgnbif_gpuMSIX_PBA_epvf_DEFAULT                0x0000
#define cfgnbif_gpuMSIX_TABLE_epf_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuMSIX_TABLE_epvf_DEFAULT              0x0000
#define cfgnbif_gpuMSI_CAP_LIST_epf_DEFAULT__GFX09      0xC005
#define cfgnbif_gpuMSI_CAP_LIST_epvf_DEFAULT            0xC005
#define cfgnbif_gpuMSI_CAP_LIST_swds_DEFAULT__GFX09     0xC005
#define cfgnbif_gpuMSI_MASK_64_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuMSI_MASK_64_epvf_DEFAULT             0x0000
#define cfgnbif_gpuMSI_MASK_epf_DEFAULT__GFX09          0x0000
#define cfgnbif_gpuMSI_MASK_epvf_DEFAULT                0x0000
#define cfgnbif_gpuMSI_MSG_ADDR_HI_epf_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuMSI_MSG_ADDR_HI_epvf_DEFAULT         0x0000
#define cfgnbif_gpuMSI_MSG_ADDR_HI_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuMSI_MSG_ADDR_LO_epf_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuMSI_MSG_ADDR_LO_epvf_DEFAULT         0x0000
#define cfgnbif_gpuMSI_MSG_ADDR_LO_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuMSI_MSG_CNTL_epf_DEFAULT__GFX09      0x0080
#define cfgnbif_gpuMSI_MSG_CNTL_swds_DEFAULT__GFX09     0x0080
#define cfgnbif_gpuMSI_MSG_DATA_64_epf_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuMSI_MSG_DATA_64_epvf_DEFAULT         0x0000
#define cfgnbif_gpuMSI_MSG_DATA_64_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuMSI_MSG_DATA_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuMSI_MSG_DATA_epvf_DEFAULT            0x0000
#define cfgnbif_gpuMSI_MSG_DATA_swds_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuMSI_PENDING_64_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuMSI_PENDING_64_epvf_DEFAULT          0x0000
#define cfgnbif_gpuMSI_PENDING_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuMSI_PENDING_epvf_DEFAULT             0x0000
#define cfgnbif_gpuPCIE_ACS_CAP_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_ACS_CAP_swds_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_ACS_CNTL_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_ACS_CNTL_swds_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_ACS_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2B01000D
#define cfgnbif_gpuPCIE_ACS_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x2F01000D
#define cfgnbif_gpuPCIE_ADV_ERR_CAP_CNTL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_ADV_ERR_CAP_CNTL_epvf_DEFAULT   0x0000
#define cfgnbif_gpuPCIE_ADV_ERR_CAP_CNTL_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x20020001
#define cfgnbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_DEFAULT 0x20020001
#define cfgnbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x20020001
#define cfgnbif_gpuPCIE_ARI_CAP_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_ARI_CAP_epvf_DEFAULT            0x0000
#define cfgnbif_gpuPCIE_ARI_CNTL_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_ARI_CNTL_epvf_DEFAULT           0x0000
#define cfgnbif_gpuPCIE_ARI_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x3301000E
#define cfgnbif_gpuPCIE_ARI_ENH_CAP_LIST_epvf_DEFAULT   0x3301000E
#define cfgnbif_gpuPCIE_ATS_CAP_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_ATS_CAP_epvf_DEFAULT            0x0000
#define cfgnbif_gpuPCIE_ATS_CNTL_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_ATS_CNTL_epvf_DEFAULT           0x0000
#define cfgnbif_gpuPCIE_ATS_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2C01000F
#define cfgnbif_gpuPCIE_ATS_ENH_CAP_LIST_epvf_DEFAULT   0x2C01000F
#define cfgnbif_gpuPCIE_BAR1_CAP_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_BAR1_CNTL_epf_DEFAULT__GFX09    0x0020
#define cfgnbif_gpuPCIE_BAR2_CAP_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_BAR2_CNTL_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_BAR3_CAP_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_BAR3_CNTL_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_BAR4_CAP_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_BAR4_CNTL_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_BAR5_CAP_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_BAR5_CNTL_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_BAR6_CAP_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_BAR6_CNTL_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_BAR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x24010015
#define cfgnbif_gpuPCIE_CAP_LIST_epf_DEFAULT__GFX09     0xA010
#define cfgnbif_gpuPCIE_CAP_LIST_epvf_DEFAULT           0xA010
#define cfgnbif_gpuPCIE_CAP_LIST_swds_DEFAULT__GFX09    0xA010
#define cfgnbif_gpuPCIE_CAP_epf_DEFAULT__GFX09          0x0002
#define cfgnbif_gpuPCIE_CAP_epvf_DEFAULT                0x0002
#define cfgnbif_gpuPCIE_CAP_swds_DEFAULT__GFX09         0x0062
#define cfgnbif_gpuPCIE_CORR_ERR_MASK_epf_DEFAULT__GFX09 0x2000
#define cfgnbif_gpuPCIE_CORR_ERR_MASK_epvf_DEFAULT      0x0000
#define cfgnbif_gpuPCIE_CORR_ERR_MASK_swds_DEFAULT__GFX09 0x2000
#define cfgnbif_gpuPCIE_CORR_ERR_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_CORR_ERR_STATUS_epvf_DEFAULT    0x0000
#define cfgnbif_gpuPCIE_CORR_ERR_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DEV_SERIAL_NUM_DW1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DEV_SERIAL_NUM_DW1_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DEV_SERIAL_NUM_DW2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DEV_SERIAL_NUM_DW2_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x15010003
#define cfgnbif_gpuPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x15010003
#define cfgnbif_gpuPCIE_DPA_CAP_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_DPA_CNTL_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_DPA_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x27010016
#define cfgnbif_gpuPCIE_DPA_LATENCY_INDICATOR_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_STATUS_epf_DEFAULT__GFX09   0x0100
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_HDR_LOG0_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_HDR_LOG0_epvf_DEFAULT           0x0000
#define cfgnbif_gpuPCIE_HDR_LOG0_swds_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_HDR_LOG1_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_HDR_LOG1_epvf_DEFAULT           0x0000
#define cfgnbif_gpuPCIE_HDR_LOG1_swds_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_HDR_LOG2_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_HDR_LOG2_epvf_DEFAULT           0x0000
#define cfgnbif_gpuPCIE_HDR_LOG2_swds_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_HDR_LOG3_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_HDR_LOG3_epvf_DEFAULT           0x0000
#define cfgnbif_gpuPCIE_HDR_LOG3_swds_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_LANE_0_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_0_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_10_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_10_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_11_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_11_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_12_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_12_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_13_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_13_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_14_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_14_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_15_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_15_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_1_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_1_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_2_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_2_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_3_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_3_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_4_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_4_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_5_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_5_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_6_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_6_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_7_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_7_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_8_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_8_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_9_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define cfgnbif_gpuPCIE_LANE_9_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define cfgnbif_gpuPCIE_LANE_ERROR_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_LANE_ERROR_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_LINK_CNTL3_epf_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuPCIE_LINK_CNTL3_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuPCIE_LTR_CAP_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_LTR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x32810018
#define cfgnbif_gpuPCIE_MC_ADDR0_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_MC_ADDR1_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuPCIE_MC_BLOCK_ALL0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_MC_BLOCK_ALL1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_MC_BLOCK_UNTRANSLATED_0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_MC_BLOCK_UNTRANSLATED_1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_MC_CAP_epf_DEFAULT__GFX09       0x003F
#define cfgnbif_gpuPCIE_MC_CNTL_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_MC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x32010012
#define cfgnbif_gpuPCIE_MC_RCV0_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_MC_RCV1_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuPCIE_OUTSTAND_PAGE_REQ_ALLOC_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PAGE_REQ_CNTL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PAGE_REQ_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2D010013
#define cfgnbif_gpuPCIE_PAGE_REQ_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PASID_CAP_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPCIE_PASID_CNTL_epf_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuPCIE_PASID_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2E01001B
#define cfgnbif_gpuPCIE_PORT_VC_CAP_REG1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_CAP_REG1_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_CAP_REG2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_CAP_REG2_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_CNTL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_CNTL_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PORT_VC_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PWR_BUDGET_CAP_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PWR_BUDGET_DATA_SELECT_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PWR_BUDGET_DATA_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_PWR_BUDGET_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x25010004
#define cfgnbif_gpuPCIE_SECONDARY_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2A010019
#define cfgnbif_gpuPCIE_SECONDARY_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x2A010019
#define cfgnbif_gpuPCIE_SRIOV_CAP_epf_DEFAULT__GFX09    0x0002
#define cfgnbif_gpuPCIE_SRIOV_CONTROL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x40010010
#define cfgnbif_gpuPCIE_SRIOV_FIRST_VF_OFFSET_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_FUNC_DEP_LINK_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_INITIAL_VFS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_NUM_VFS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_SYSTEM_PAGE_SIZE_epf_DEFAULT__GFX09 0x0001
#define cfgnbif_gpuPCIE_SRIOV_TOTAL_VFS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_3_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_4_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_5_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_DEVICE_ID_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_SRIOV_VF_STRIDE_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG0_epvf_DEFAULT    0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG0_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG1_epvf_DEFAULT    0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG1_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG2_epvf_DEFAULT    0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG2_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG3_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG3_epvf_DEFAULT    0x0000
#define cfgnbif_gpuPCIE_TLP_PREFIX_LOG3_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TPH_REQR_CAP_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TPH_REQR_CNTL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_TPH_REQR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2F010017
#define cfgnbif_gpuPCIE_UNCORR_ERR_MASK_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_UNCORR_ERR_MASK_epvf_DEFAULT    0x0000
#define cfgnbif_gpuPCIE_UNCORR_ERR_MASK_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_UNCORR_ERR_SEVERITY_epf_DEFAULT__GFX09 0x462030
#define cfgnbif_gpuPCIE_UNCORR_ERR_SEVERITY_epvf_DEFAULT 0x0000
#define cfgnbif_gpuPCIE_UNCORR_ERR_SEVERITY_swds_DEFAULT__GFX09 0x462030
#define cfgnbif_gpuPCIE_UNCORR_ERR_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_UNCORR_ERR_STATUS_epvf_DEFAULT  0x0000
#define cfgnbif_gpuPCIE_UNCORR_ERR_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC0_RESOURCE_CAP_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC0_RESOURCE_CAP_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC0_RESOURCE_CNTL_epf_DEFAULT__GFX09 0x800000FF
#define cfgnbif_gpuPCIE_VC0_RESOURCE_CNTL_swds_DEFAULT__GFX09 0x800000FF
#define cfgnbif_gpuPCIE_VC0_RESOURCE_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC0_RESOURCE_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC1_RESOURCE_CAP_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC1_RESOURCE_CAP_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC1_RESOURCE_CNTL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC1_RESOURCE_CNTL_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC1_RESOURCE_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC1_RESOURCE_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x14010002
#define cfgnbif_gpuPCIE_VC_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x14010002
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC1_epvf_DEFAULT   0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC1_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC2_epvf_DEFAULT   0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC2_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf_DEFAULT__GFX09 0x1000B
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x1101000B
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_DEFAULT 0x1101000B
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x1101000B
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf_DEFAULT__GFX09 0xF020002
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_epf_DEFAULT__GFX09 0x1010001
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_epvf_DEFAULT 0x1010001
#define cfgnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_swds_DEFAULT__GFX09 0x1010001
#define cfgnbif_gpuPMI_CAP_LIST_epf_DEFAULT__GFX09      0x0001
#define cfgnbif_gpuPMI_CAP_LIST_swds_DEFAULT__GFX09     0x5801
#define cfgnbif_gpuPMI_CAP_epf_DEFAULT__GFX09           0x0003
#define cfgnbif_gpuPMI_CAP_swds_DEFAULT__GFX09          0x0003
#define cfgnbif_gpuPMI_STATUS_CNTL_epf_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuPMI_STATUS_CNTL_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuPREF_BASE_LIMIT_swds_DEFAULT__GFX09  0x10001
#define cfgnbif_gpuPREF_BASE_UPPER_swds_DEFAULT__GFX09  0x0000
#define cfgnbif_gpuPREF_LIMIT_UPPER_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuPROG_INTERFACE_epf_DEFAULT__GFX09    0x0000
#define cfgnbif_gpuPROG_INTERFACE_epvf_DEFAULT          0x0000
#define cfgnbif_gpuPROG_INTERFACE_swds_DEFAULT__GFX09   0x0000
#define cfgnbif_gpuREVISION_ID_epf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuREVISION_ID_epvf_DEFAULT             0x0000
#define cfgnbif_gpuREVISION_ID_swds_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuROM_BASE_ADDR_epf_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuROM_BASE_ADDR_epvf_DEFAULT           0x0000
#define cfgnbif_gpuSECONDARY_STATUS_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuSHADOW_BASE_ADDR_1_DEFAULT           0x0000
#define cfgnbif_gpuSHADOW_BASE_ADDR_2_DEFAULT           0x0000
#define cfgnbif_gpuSHADOW_COMMAND_DEFAULT               0x0000
#define cfgnbif_gpuSHADOW_IO_BASE_LIMIT_DEFAULT         0x0000
#define cfgnbif_gpuSHADOW_IO_BASE_LIMIT_HI_DEFAULT      0x0000
#define cfgnbif_gpuSHADOW_IRQ_BRIDGE_CNTL_DEFAULT       0x0000
#define cfgnbif_gpuSHADOW_MEM_BASE_LIMIT_DEFAULT        0x0000
#define cfgnbif_gpuSHADOW_PREF_BASE_LIMIT_DEFAULT       0x10001
#define cfgnbif_gpuSHADOW_PREF_BASE_UPPER_DEFAULT       0x0000
#define cfgnbif_gpuSHADOW_PREF_LIMIT_UPPER_DEFAULT      0x0000
#define cfgnbif_gpuSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x0000
#define cfgnbif_gpuSLOT_CAP2_epf_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuSLOT_CAP2_epvf_DEFAULT               0x0000
#define cfgnbif_gpuSLOT_CAP2_swds_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuSLOT_CAP_swds_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuSLOT_CNTL2_epf_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuSLOT_CNTL2_epvf_DEFAULT              0x0000
#define cfgnbif_gpuSLOT_CNTL2_swds_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuSLOT_CNTL_swds_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuSLOT_STATUS2_epf_DEFAULT__GFX09      0x0000
#define cfgnbif_gpuSLOT_STATUS2_epvf_DEFAULT            0x0000
#define cfgnbif_gpuSLOT_STATUS2_swds_DEFAULT__GFX09     0x0000
#define cfgnbif_gpuSLOT_STATUS_swds_DEFAULT__GFX09      0x0040
#define cfgnbif_gpuSSID_CAP_LIST_swds_DEFAULT__GFX09    0x000D
#define cfgnbif_gpuSSID_CAP_swds_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuSTATUS_epf_DEFAULT__GFX09            0x0010
#define cfgnbif_gpuSTATUS_epvf_DEFAULT                  0x0010
#define cfgnbif_gpuSTATUS_swds_DEFAULT__GFX09           0x0010
#define cfgnbif_gpuSUB_BUS_NUMBER_LATENCY_swds_DEFAULT__GFX09 0x0000
#define cfgnbif_gpuSUB_CLASS_epf_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuSUB_CLASS_epvf_DEFAULT               0x0000
#define cfgnbif_gpuSUB_CLASS_swds_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuVENDOR_CAP_LIST_epf_DEFAULT__GFX09   0x85009
#define cfgnbif_gpuVENDOR_ID_epf_DEFAULT__GFX09         0x0000
#define cfgnbif_gpuVENDOR_ID_epvf_DEFAULT               0xFFFF
#define cfgnbif_gpuVENDOR_ID_swds_DEFAULT__GFX09        0x0000
#define ionbif_gpuMM_DATA_DEFAULT                       0x0000
#define ionbif_gpuMM_INDEX_DEFAULT                      0x0000
#define ionbif_gpuMM_INDEX_HI_DEFAULT                   0x0000
#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT              0x0000
#define mmATC_ATS_FAULT_CNTL_DEFAULT                    0x01FF
#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT             0x0000
#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT            0x0000
#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT             0x0000
#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT              0x0000
#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT            0x0000
#define mmATC_ATS_SDPPORT_CNTL_DEFAULT                  0x3FFA210
#define mmATC_ATS_STATUS_DEFAULT                        0x0000
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT        0x0000
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT      0x0000
#define mmATC_ATS_VMID_STATUS_DEFAULT                   0x0000
#define mmATC_L2_CACHE_DATA0_DEFAULT__GFX09             0x0000
#define mmATC_L2_CACHE_DATA1_DEFAULT__GFX09             0x0000
#define mmATC_L2_CACHE_DATA2_DEFAULT__GFX09             0x0000
#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT__GFX09           0x0080
#define mmATC_L2_CNTL2_DEFAULT__GFX09                   0x0100
#define mmATC_L2_CNTL3_DEFAULT__GFX09                   0x01F8
#define mmATC_L2_CNTL_DEFAULT__GFX09                    0x01C9
#define mmATC_L2_MEM_POWER_LS_DEFAULT__GFX09            0x0208
#define mmATC_L2_MISC_CG_DEFAULT__GFX09                 0x0200
#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT__GFX09        0x0000
#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT__GFX09        0x0000
#define mmATC_L2_PERFCOUNTER_HI_DEFAULT__GFX09          0x0000
#define mmATC_L2_PERFCOUNTER_LO_DEFAULT__GFX09          0x0000
#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT__GFX09   0x4000000
#define mmATC_L2_STATUS2_DEFAULT__GFX09                 0x0000
#define mmATC_L2_STATUS_DEFAULT__GFX09                  0x0000
#define mmATC_PERFCOUNTER0_CFG_DEFAULT                  0x0000
#define mmATC_PERFCOUNTER1_CFG_DEFAULT                  0x0000
#define mmATC_PERFCOUNTER2_CFG_DEFAULT                  0x0000
#define mmATC_PERFCOUNTER3_CFG_DEFAULT                  0x0000
#define mmATC_PERFCOUNTER_HI_DEFAULT                    0x0000
#define mmATC_PERFCOUNTER_LO_DEFAULT                    0x0000
#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT             0x4000000
#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT              0xFFFFFFFF
#define mmATC_VMID0_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID10_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID11_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID12_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID13_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID14_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID15_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID16_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID17_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID18_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID19_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID1_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID20_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID21_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID22_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID23_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID24_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID25_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID26_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID27_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID28_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID29_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID2_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID30_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID31_PASID_MAPPING_DEFAULT              0x0000
#define mmATC_VMID3_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID4_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID5_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID6_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID7_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID8_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID9_PASID_MAPPING_DEFAULT               0x0000
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT  0x0000
#define mmATHUB_COMMAND_DEFAULT                         0x0000
#define mmATHUB_IH_CREDIT_DEFAULT                       0x20002
#define mmATHUB_MEM_POWER_LS_DEFAULT                    0x0208
#define mmATHUB_PCIE_ATS_CNTL_DEFAULT                   0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT             0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT             0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT             0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT             0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT             0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT             0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT              0x0000
#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT              0x0000
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT    0x0000
#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT              0x0000
#define mmATHUB_PCIE_PASID_CNTL_DEFAULT                 0x0000
#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT            0x0000
#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT           0x0000
#define mmATS_IH_CREDIT_DEFAULT                         0x150002
#define mmBCI_DEBUG_READ_DEFAULT                        0xCDCDCD
#define mmCB_BLEND0_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND1_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND2_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND3_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND4_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND5_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND6_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND7_CONTROL_DEFAULT                     0x4DCD0DCD
#define mmCB_BLEND_ALPHA_DEFAULT                        0xCDCDCDCD
#define mmCB_BLEND_BLUE_DEFAULT                         0xCDCDCDCD
#define mmCB_BLEND_GREEN_DEFAULT                        0xCDCDCDCD
#define mmCB_BLEND_RED_DEFAULT                          0xCDCDCDCD
#define mmCB_CGTT_SCLK_CTRL_DEFAULT                     0x0100
#define mmCB_COLOR0_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR0_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR0_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR0_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR0_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR0_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR1_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR1_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR1_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR1_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR1_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR1_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR2_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR2_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR2_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR2_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR2_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR2_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR3_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR3_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR3_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR3_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR3_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR3_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR4_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR4_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR4_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR4_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR4_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR4_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR5_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR5_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR5_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR5_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR5_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR5_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR6_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR6_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR6_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR6_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR6_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR6_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR7_ATTRIB2_DEFAULT                     0xCDCDCDCD
#define mmCB_COLOR7_BASE_DEFAULT                        0xCDCDCDCD
#define mmCB_COLOR7_BASE_EXT_DEFAULT                    0x00CD
#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT                 0xCDCDCDCD
#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR7_CMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR7_DCC_BASE_DEFAULT                    0xCDCDCDCD
#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT                0x00CD
#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT              0x00CD
#define mmCB_COLOR7_FMASK_DEFAULT                       0xCDCDCDCD
#define mmCB_COLOR_CONTROL_DEFAULT                      0xCD0049
#define mmCB_HW_CONTROL_1_DEFAULT                       0x10000000
#define mmCB_HW_MEM_ARBITER_RD_DEFAULT                  0x29000
#define mmCB_HW_MEM_ARBITER_WR_DEFAULT                  0x29000
#define mmCB_MRT0_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT1_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT2_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT3_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT4_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT5_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT6_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_MRT7_EPITCH_DEFAULT__GFX09                 0xCDCD
#define mmCB_PERFCOUNTER0_HI_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER0_LO_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT               0x0000
#define mmCB_PERFCOUNTER0_SELECT_DEFAULT                0x0000
#define mmCB_PERFCOUNTER1_HI_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER1_LO_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER1_SELECT_DEFAULT                0x0000
#define mmCB_PERFCOUNTER2_HI_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER2_LO_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER2_SELECT_DEFAULT                0x0000
#define mmCB_PERFCOUNTER3_HI_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER3_LO_DEFAULT                    0xCDCDCDCD
#define mmCB_PERFCOUNTER3_SELECT_DEFAULT                0x0000
#define mmCB_PERFCOUNTER_FILTER_DEFAULT                 0x0000
#define mmCB_SHADER_MASK_DEFAULT                        0xCDCDCDCD
#define mmCB_TARGET_MASK_DEFAULT                        0xCDCDCDCD
#define mmCC_GC_EDC_CONFIG_DEFAULT                      0x0000
#define mmCC_GC_PRIM_CONFIG_DEFAULT                     0x0000
#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT              0x0000
#define mmCC_RB_BACKEND_DISABLE_DEFAULT                 0x0000
#define mmCC_RB_DAISY_CHAIN_DEFAULT                     0x76543210
#define mmCC_RB_REDUNDANCY_DEFAULT                      0x0000
#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x40007
#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT__GFX09      0x30002
#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT__GFX09         0x10000
#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT__GFX09         0x60005
#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT__GFX09      0x0007
#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT__GFX09        0x000A
#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT__GFX09      0x90008
#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT__GFX09      0x30002
#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT__GFX09         0x10000
#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT__GFX09         0x60005
#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT__GFX09      0x0007
#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT__GFX09        0x000A
#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT__GFX09      0x90008
#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT__GFX09      0x30002
#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT__GFX09         0x10000
#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT__GFX09         0x60005
#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT__GFX09      0x40007
#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT__GFX09        0x000A
#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT__GFX09      0x90008
#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT__GFX09      0x30002
#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT__GFX09         0x10000
#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT__GFX09         0x60005
#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT__GFX09      0x0007
#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT__GFX09        0x000A
#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT__GFX09      0x90008
#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT__GFX09      0x30002
#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT__GFX09         0x10000
#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT__GFX09         0x60005
#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT__GFX09      0x0007
#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT__GFX09        0x000A
#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT__GFX09      0x90008
#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT__GFX09      0x30002
#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT__GFX09         0x10000
#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT__GFX09         0x60005
#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT__GFX09      0x40007
#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT__GFX09        0x000A
#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT__GFX09      0x90008
#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x0007
#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT__GFX09         0x0001
#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x0007
#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x40007
#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x0007
#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x0007
#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x40007
#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x0007
#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x0007
#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT__GFX09       0x30002
#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT__GFX09          0x10000
#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT__GFX09          0x60005
#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT__GFX09       0x40007
#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT__GFX09         0x000A
#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT__GFX09       0x90008
#define mmCGTS_RD_CTRL_REG_DEFAULT                      0x0000
#define mmCGTS_RD_REG_DEFAULT                           0x0000
#define mmCGTS_SM_CTRL_REG_DEFAULT__GFX09               0x600200
#define mmCGTS_TCC_DISABLE_DEFAULT                      0x0000
#define mmCGTS_USER_TCC_DISABLE_DEFAULT                 0x0000
#define mmCGTT_BCI_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_CPC_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_CPF_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_CP_CLK_CTRL_DEFAULT                      0x0100
#define mmCGTT_GDS_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_IA_CLK_CTRL_DEFAULT                      0x6000100
#define mmCGTT_PA_CLK_CTRL_DEFAULT                      0x0100
#define mmCGTT_PC_CLK_CTRL_DEFAULT                      0x0100
#define mmCGTT_RLC_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_ROM_CLK_CTRL0_DEFAULT                    0xC0000100
#define mmCGTT_SC_CLK_CTRL0_DEFAULT                     0x0100
#define mmCGTT_SC_CLK_CTRL1_DEFAULT                     0x0100
#define mmCGTT_SPI_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_SQG_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_SQ_CLK_CTRL_DEFAULT                      0x0100
#define mmCGTT_SX_CLK_CTRL0_DEFAULT                     0xC100
#define mmCGTT_SX_CLK_CTRL1_DEFAULT                     0xC100
#define mmCGTT_SX_CLK_CTRL2_DEFAULT                     0xC100
#define mmCGTT_SX_CLK_CTRL3_DEFAULT                     0xC100
#define mmCGTT_SX_CLK_CTRL4_DEFAULT                     0xC100
#define mmCGTT_TCI_CLK_CTRL_DEFAULT                     0x0100
#define mmCGTT_TCPF_CLK_CTRL_DEFAULT                    0x0100
#define mmCGTT_TCPI_CLK_CTRL_DEFAULT                    0x0100
#define mmCGTT_VGT_CLK_CTRL_DEFAULT                     0x18100
#define mmCGTT_WD_CLK_CTRL_DEFAULT                      0x18100
#define mmCOHER_DEST_BASE_0_DEFAULT                     0x0000
#define mmCOHER_DEST_BASE_1_DEFAULT                     0x0000
#define mmCOHER_DEST_BASE_2_DEFAULT                     0x0000
#define mmCOHER_DEST_BASE_3_DEFAULT                     0x0000
#define mmCOHER_DEST_BASE_HI_0_DEFAULT                  0x0000
#define mmCOHER_DEST_BASE_HI_1_DEFAULT                  0x0000
#define mmCOHER_DEST_BASE_HI_2_DEFAULT                  0x0000
#define mmCOHER_DEST_BASE_HI_3_DEFAULT                  0x0000
#define mmCOMPUTE_DIM_X_DEFAULT                         0xCDCDCDCD
#define mmCOMPUTE_DIM_Y_DEFAULT                         0xCDCDCDCD
#define mmCOMPUTE_DIM_Z_DEFAULT                         0xCDCDCDCD
#define mmCOMPUTE_DISPATCH_ID_DEFAULT                   0x0000
#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT          0x00CD
#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT          0xCDCDCDCD
#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT      0x00CD
#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT      0xCDCDCDCD
#define mmCOMPUTE_NOWHERE_DEFAULT                       0xCDCDCDCD
#define mmCOMPUTE_NUM_THREAD_X_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT              0x0000
#define mmCOMPUTE_PGM_HI_DEFAULT                        0x00CD
#define mmCOMPUTE_PGM_LO_DEFAULT                        0xCDCDCDCD
#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT           0x0001
#define mmCOMPUTE_RELAUNCH_DEFAULT                      0xCDCDCDCD
#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT               0x5CDC1CD
#define mmCOMPUTE_RESTART_X_DEFAULT                     0x0000
#define mmCOMPUTE_RESTART_Y_DEFAULT                     0x0000
#define mmCOMPUTE_RESTART_Z_DEFAULT                     0x0000
#define mmCOMPUTE_START_X_DEFAULT                       0xCDCDCDCD
#define mmCOMPUTE_START_Y_DEFAULT                       0xCDCDCDCD
#define mmCOMPUTE_START_Z_DEFAULT                       0xCDCDCDCD
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT        0xFFFFFFFF
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT        0xFFFFFFFF
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT        0xFFFFFFFF
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT        0xFFFFFFFF
#define mmCOMPUTE_THREADGROUP_ID_DEFAULT                0x0000
#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT           0x0000
#define mmCOMPUTE_TMPRING_SIZE_DEFAULT                  0x1CDCDCD
#define mmCOMPUTE_USER_DATA_0_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_10_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_11_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_12_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_13_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_14_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_15_DEFAULT                  0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_1_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_2_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_3_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_4_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_5_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_6_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_7_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_8_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_USER_DATA_9_DEFAULT                   0xCDCDCDCD
#define mmCOMPUTE_VMID_DEFAULT                          0x000D
#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT          0xCDCD
#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT          0xCDCDCDCD
#define mmCPC_INT_ADDR_DEFAULT                          0x0000
#define mmCPC_INT_CNTL_DEFAULT                          0x0000
#define mmCPC_INT_CNTX_ID_DEFAULT                       0x0000
#define mmCPC_INT_INFO_DEFAULT                          0x0000
#define mmCPC_INT_PASID_DEFAULT                         0x0000
#define mmCPC_INT_STATUS_DEFAULT                        0x0000
#define mmCPC_LATENCY_STATS_DATA_DEFAULT                0x0000
#define mmCPC_LATENCY_STATS_SELECT_DEFAULT              0x0000
#define mmCPC_PERFCOUNTER0_HI_DEFAULT                   0x0000
#define mmCPC_PERFCOUNTER0_LO_DEFAULT                   0x0000
#define mmCPC_PERFCOUNTER1_HI_DEFAULT                   0x0000
#define mmCPC_PERFCOUNTER1_LO_DEFAULT                   0x0000
#define mmCPC_UTCL1_CNTL_DEFAULT                        0x0080
#define mmCPC_UTCL1_ERROR_DEFAULT                       0x0000
#define mmCPC_UTCL1_STATUS_DEFAULT                      0x0000
#define mmCPF_LATENCY_STATS_DATA_DEFAULT                0x0000
#define mmCPF_LATENCY_STATS_SELECT_DEFAULT              0x0000
#define mmCPF_PERFCOUNTER0_HI_DEFAULT                   0x0000
#define mmCPF_PERFCOUNTER0_LO_DEFAULT                   0x0000
#define mmCPF_PERFCOUNTER1_HI_DEFAULT                   0x0000
#define mmCPF_PERFCOUNTER1_LO_DEFAULT                   0x0000
#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT     0x0000
#define mmCPF_UTCL1_CNTL_DEFAULT                        0x0080
#define mmCPF_UTCL1_STATUS_DEFAULT                      0x0000
#define mmCPG_LATENCY_STATS_DATA_DEFAULT                0x0000
#define mmCPG_LATENCY_STATS_SELECT_DEFAULT              0x0000
#define mmCPG_PERFCOUNTER0_HI_DEFAULT                   0x0000
#define mmCPG_PERFCOUNTER0_LO_DEFAULT                   0x0000
#define mmCPG_PERFCOUNTER1_HI_DEFAULT                   0x0000
#define mmCPG_PERFCOUNTER1_LO_DEFAULT                   0x0000
#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT     0x0000
#define mmCPG_UTCL1_CNTL_DEFAULT                        0x0080
#define mmCPG_UTCL1_ERROR_DEFAULT                       0x0000
#define mmCPG_UTCL1_STATUS_DEFAULT                      0x0000
#define mmCP_APPEND_ADDR_LO_DEFAULT                     0xCDCDCDCC
#define mmCP_APPEND_DATA_HI_DEFAULT                     0xCDCDCDCD
#define mmCP_APPEND_DATA_LO_DEFAULT                     0xCDCDCDCD
#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT            0xCDCDCDCD
#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT            0xCDCDCDCD
#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT            0xCDCDCDCD
#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT            0xCDCDCDCD
#define mmCP_AQL_SMM_STATUS_DEFAULT                     0x0000
#define mmCP_ATOMIC_PREOP_HI_DEFAULT                    0xCDCDCDCD
#define mmCP_ATOMIC_PREOP_LO_DEFAULT                    0xCDCDCDCD
#define mmCP_BUSY_STAT_DEFAULT                          0x4CC5C1
#define mmCP_CE_COMPARE_COUNT_DEFAULT                   0x0000
#define mmCP_CE_COMPLETION_STATUS_DEFAULT               0x0000
#define mmCP_CE_COUNTER_DEFAULT                         0x0000
#define mmCP_CE_DE_COUNT_DEFAULT                        0x0000
#define mmCP_CE_HEADER_DUMP_DEFAULT                     0xCDCDCDCD
#define mmCP_CE_IB1_BASE_HI_DEFAULT                     0xCDCD
#define mmCP_CE_IB1_BASE_LO_DEFAULT                     0xCDCDCDCC
#define mmCP_CE_IB1_BUFSZ_DEFAULT                       0x0000
#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT                   0x0000
#define mmCP_CE_IB1_OFFSET_DEFAULT                      0x0000
#define mmCP_CE_IB2_BASE_HI_DEFAULT                     0xCDCD
#define mmCP_CE_IB2_BASE_LO_DEFAULT                     0xCDCDCDCC
#define mmCP_CE_IB2_BUFSZ_DEFAULT                       0x0000
#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT                   0x0000
#define mmCP_CE_IB2_OFFSET_DEFAULT                      0x0000
#define mmCP_CE_INIT_BASE_HI_DEFAULT                    0xCDCD
#define mmCP_CE_INIT_BASE_LO_DEFAULT                    0xCDCDCDC0
#define mmCP_CE_INIT_BUFSZ_DEFAULT                      0x0000
#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT                  0x0000
#define mmCP_CE_INSTR_PNTR_DEFAULT                      0x0000
#define mmCP_CE_INTR_ROUTINE_START_DEFAULT              0x0002
#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT              0x0000
#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT           0x0000
#define mmCP_CE_PRGRM_CNTR_START_DEFAULT                0x0000
#define mmCP_CE_RB_OFFSET_DEFAULT__GFX09                0x0000
#define mmCP_CE_UCODE_ADDR_DEFAULT                      0x0000
#define mmCP_CE_UCODE_DATA_DEFAULT                      0xCDCDCDCD
#define mmCP_CMD_DATA_DEFAULT                           0xCDCDCDCD
#define mmCP_CMD_INDEX_DEFAULT                          0x505CD
#define mmCP_CNTX_STAT_DEFAULT                          0x4DC005CD
#define mmCP_COHER_BASE_DEFAULT                         0x0000
#define mmCP_COHER_BASE_HI_DEFAULT                      0x0000
#define mmCP_COHER_CNTL_DEFAULT                         0x0000
#define mmCP_COHER_SIZE_DEFAULT                         0x0000
#define mmCP_COHER_SIZE_HI_DEFAULT                      0x0000
#define mmCP_COHER_START_DELAY_DEFAULT                  0x0020
#define mmCP_COHER_STATUS_DEFAULT                       0x0000
#define mmCP_CONTEXT_CNTL_DEFAULT                       0x750075
#define mmCP_CPC_BUSY_STAT_DEFAULT                      0xDCD0DCD
#define mmCP_CPC_GFX_CNTL_DEFAULT                       0x0000
#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT                0x0008
#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT                0x0002
#define mmCP_CPC_IC_BASE_HI_DEFAULT                     0xCDCD
#define mmCP_CPC_IC_BASE_LO_DEFAULT                     0xCDCDC000
#define mmCP_CPC_IC_OP_CNTL_DEFAULT                     0x0000
#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT                 0x1020
#define mmCP_CPC_SCRATCH_DATA_DEFAULT                   0xCDCDCDCD
#define mmCP_CPC_SCRATCH_INDEX_DEFAULT                  0x0000
#define mmCP_CPC_STALLED_STAT1_DEFAULT                  0x1C50548
#define mmCP_CPF_DEBUG_DEFAULT                          0x0000
#define mmCP_CPF_STALLED_STAT1_DEFAULT                  0x0DCD
#define mmCP_CSF_STAT_DEFAULT                           0x1CD00
#define mmCP_DEVICE_ID_DEFAULT                          0x0000
#define mmCP_DE_CE_COUNT_DEFAULT                        0x0000
#define mmCP_DE_DE_COUNT_DEFAULT                        0x0000
#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT                0x0000
#define mmCP_DFY_ADDR_HI_DEFAULT                        0x0000
#define mmCP_DFY_ADDR_LO_DEFAULT                        0x0000
#define mmCP_DFY_CMD_DEFAULT                            0x0000
#define mmCP_DFY_CNTL_DEFAULT                           0x0000
#define mmCP_DFY_DATA_0_DEFAULT                         0x0000
#define mmCP_DFY_DATA_10_DEFAULT                        0x0000
#define mmCP_DFY_DATA_11_DEFAULT                        0x0000
#define mmCP_DFY_DATA_12_DEFAULT                        0x0000
#define mmCP_DFY_DATA_13_DEFAULT                        0x0000
#define mmCP_DFY_DATA_14_DEFAULT                        0x0000
#define mmCP_DFY_DATA_15_DEFAULT                        0x0000
#define mmCP_DFY_DATA_1_DEFAULT                         0x0000
#define mmCP_DFY_DATA_2_DEFAULT                         0x0000
#define mmCP_DFY_DATA_3_DEFAULT                         0x0000
#define mmCP_DFY_DATA_4_DEFAULT                         0x0000
#define mmCP_DFY_DATA_5_DEFAULT                         0x0000
#define mmCP_DFY_DATA_6_DEFAULT                         0x0000
#define mmCP_DFY_DATA_7_DEFAULT                         0x0000
#define mmCP_DFY_DATA_8_DEFAULT                         0x0000
#define mmCP_DFY_DATA_9_DEFAULT                         0x0000
#define mmCP_DFY_STAT_DEFAULT                           0x0000
#define mmCP_DISPATCH_INDR_ADDR_DEFAULT                 0x0000
#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT              0x0000
#define mmCP_DMA_ME_COMMAND_DEFAULT                     0x0000
#define mmCP_DMA_ME_CONTROL_DEFAULT                     0x0000
#define mmCP_DMA_ME_DST_ADDR_DEFAULT                    0x0000
#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT                 0x0000
#define mmCP_DMA_ME_SRC_ADDR_DEFAULT                    0x0000
#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT                 0x0000
#define mmCP_DMA_PFP_COMMAND_DEFAULT                    0x0000
#define mmCP_DMA_PFP_CONTROL_DEFAULT                    0x0000
#define mmCP_DMA_PFP_DST_ADDR_DEFAULT                   0x0000
#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT                0x0000
#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT                   0x0000
#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT                0x0000
#define mmCP_DMA_READ_TAGS_DEFAULT                      0x0000
#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT                0x0000
#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT             0x0000
#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT                0x0000
#define mmCP_DRAW_OBJECT_DEFAULT                        0x0000
#define mmCP_DRAW_WINDOW_CNTL_DEFAULT                   0x0007
#define mmCP_DRAW_WINDOW_HI_DEFAULT                     0x0000
#define mmCP_DRAW_WINDOW_LO_DEFAULT                     0x0000
#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT                0x0000
#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT                0x0000
#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT          0xCDCDCDCD
#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT          0xCDCDCDCD
#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT          0xCDCDCDCD
#define mmCP_EOPQ_WAIT_TIME_DEFAULT                     0x052C
#define mmCP_EOP_DONE_ADDR_HI_DEFAULT                   0xCDCD
#define mmCP_EOP_DONE_ADDR_LO_DEFAULT                   0xCDCDCDCC
#define mmCP_EOP_DONE_CNTX_ID_DEFAULT                   0xCDCDCDCD
#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT                 0xC5010000
#define mmCP_EOP_DONE_DATA_HI_DEFAULT                   0xCDCDCDCD
#define mmCP_EOP_DONE_DATA_LO_DEFAULT                   0xCDCDCDCD
#define mmCP_EOP_LAST_FENCE_HI_DEFAULT                  0xCDCDCDCD
#define mmCP_EOP_LAST_FENCE_LO_DEFAULT                  0xCDCDCDCD
#define mmCP_FATAL_ERROR_DEFAULT                        0x0000
#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT               0xCDCDCDCD
#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT               0xCDCDCDCD
#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT               0xCDCDCDCD
#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT               0xCDCDCDCD
#define mmCP_GDS_BKUP_ADDR_DEFAULT                      0x0000
#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT                   0x0000
#define mmCP_GFX_ERROR_DEFAULT                          0x0000
#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT                  0x0000
#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT               0x0000
#define mmCP_GFX_MQD_CONTROL_DEFAULT                    0x0100
#define mmCP_GRBM_FREE_COUNT_DEFAULT                    0x80808
#define mmCP_HPD_ROQ_OFFSETS_DEFAULT                    0x200604
#define mmCP_HPD_STATUS0_DEFAULT                        0x1000000
#define mmCP_HPD_UTCL1_CNTL_DEFAULT                     0x0000
#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT               0x0000
#define mmCP_HPD_UTCL1_ERROR_DEFAULT                    0x0000
#define mmCP_HQD_ACTIVE_DEFAULT                         0x0000
#define mmCP_HQD_AQL_CONTROL_DEFAULT                    0x0000
#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT               0x0000
#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT               0x0000
#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT               0x0000
#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT               0x0000
#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT              0x0000
#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT                0x0000
#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT          0x0000
#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT          0x0000
#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT               0x0000
#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT                  0x0000
#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT                0x0000
#define mmCP_HQD_DMA_OFFLOAD_DEFAULT                    0x0000
#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT                  0x0000
#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT               0x0000
#define mmCP_HQD_EOP_CONTROL_DEFAULT                    0x0006
#define mmCP_HQD_EOP_EVENTS_DEFAULT                     0x0000
#define mmCP_HQD_EOP_RPTR_DEFAULT                       0x40000000
#define mmCP_HQD_EOP_WPTR_DEFAULT                       0x7F8000
#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT                   0x0000
#define mmCP_HQD_ERROR_DEFAULT                          0x0000
#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT             0x0000
#define mmCP_HQD_GFX_CONTROL_DEFAULT                    0x0000
#define mmCP_HQD_GFX_STATUS_DEFAULT                     0x0000
#define mmCP_HQD_HQ_CONTROL0_DEFAULT                    0x0000
#define mmCP_HQD_HQ_CONTROL1_DEFAULT                    0x0000
#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT                  0x0000
#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT                  0x0000
#define mmCP_HQD_HQ_STATUS0_DEFAULT                     0x40000000
#define mmCP_HQD_HQ_STATUS1_DEFAULT                     0x0000
#define mmCP_HQD_IB_BASE_ADDR_DEFAULT                   0x0000
#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT                0x0000
#define mmCP_HQD_IB_CONTROL_DEFAULT                     0x300000
#define mmCP_HQD_IB_RPTR_DEFAULT                        0x0000
#define mmCP_HQD_IQ_RPTR_DEFAULT                        0x0000
#define mmCP_HQD_IQ_TIMER_DEFAULT                       0x0000
#define mmCP_HQD_MSG_TYPE_DEFAULT                       0x0000
#define mmCP_HQD_OFFLOAD_DEFAULT                        0x0000
#define mmCP_HQD_PERSISTENT_STATE_DEFAULT               0xBE05301
#define mmCP_HQD_PIPE_PRIORITY_DEFAULT                  0x0000
#define mmCP_HQD_PQ_BASE_DEFAULT                        0x0000
#define mmCP_HQD_PQ_BASE_HI_DEFAULT                     0x0000
#define mmCP_HQD_PQ_CONTROL_DEFAULT                     0x308509
#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT            0x0000
#define mmCP_HQD_PQ_RPTR_DEFAULT                        0x0000
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT            0x0000
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT         0x0000
#define mmCP_HQD_PQ_WPTR_HI_DEFAULT                     0x0000
#define mmCP_HQD_PQ_WPTR_LO_DEFAULT                     0x0000
#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT              0x0000
#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT           0x0000
#define mmCP_HQD_QUANTUM_DEFAULT                        0x0000
#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT                 0x0000
#define mmCP_HQD_SEMA_CMD_DEFAULT                       0x0000
#define mmCP_HQD_VMID_DEFAULT                           0x0000
#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT                0x0000
#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT                  0x0000
#define mmCP_HYP_CE_UCODE_DATA_DEFAULT                  0xCDCDCDCD
#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT                0xCDCDCDCD
#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT                0xCDCDCDCD
#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT                  0x0000
#define mmCP_HYP_ME_UCODE_DATA_DEFAULT                  0xCDCDCDCD
#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT                 0x0000
#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT                 0xCDCDCDCD
#define mmCP_IB1_BASE_HI_DEFAULT                        0xCDCD
#define mmCP_IB1_BASE_LO_DEFAULT                        0xCDCDCDCC
#define mmCP_IB1_BUFSZ_DEFAULT                          0x0000
#define mmCP_IB1_CMD_BUFSZ_DEFAULT                      0x0000
#define mmCP_IB1_OFFSET_DEFAULT                         0xDCDCD
#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT                 0x0000
#define mmCP_IB1_PREAMBLE_END_DEFAULT                   0x0000
#define mmCP_IB2_BASE_HI_DEFAULT                        0xCDCD
#define mmCP_IB2_BASE_LO_DEFAULT                        0xCDCDCDCC
#define mmCP_IB2_BUFSZ_DEFAULT                          0x0000
#define mmCP_IB2_CMD_BUFSZ_DEFAULT                      0x0000
#define mmCP_IB2_OFFSET_DEFAULT                         0xDCDCD
#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT                 0x0000
#define mmCP_IB2_PREAMBLE_END_DEFAULT                   0x0000
#define mmCP_INDEX_BASE_ADDR_DEFAULT                    0x0000
#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT                 0x0000
#define mmCP_INDEX_TYPE_DEFAULT                         0x0000
#define mmCP_INT_CNTL_DEFAULT                           0x0000
#define mmCP_INT_CNTL_RING0_DEFAULT                     0x0000
#define mmCP_INT_CNTL_RING1_DEFAULT                     0x0000
#define mmCP_INT_CNTL_RING2_DEFAULT                     0x0000
#define mmCP_INT_STATUS_DEFAULT                         0x0000
#define mmCP_INT_STATUS_RING0_DEFAULT                   0x0000
#define mmCP_INT_STATUS_RING1_DEFAULT                   0x0000
#define mmCP_INT_STATUS_RING2_DEFAULT                   0x0000
#define mmCP_INT_STAT_DEBUG_DEFAULT                     0x0000
#define mmCP_IQ_WAIT_TIME1_DEFAULT                      0x40404040
#define mmCP_IQ_WAIT_TIME2_DEFAULT                      0x40404040
#define mmCP_MAX_CONTEXT_DEFAULT                        0x0007
#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME0_PIPE0_VMID_DEFAULT                     0x0000
#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME0_PIPE1_VMID_DEFAULT                     0x0000
#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT             0x8081020
#define mmCP_ME1_INT_STAT_DEBUG_DEFAULT                 0x0000
#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT             0x8081020
#define mmCP_ME2_INT_STAT_DEBUG_DEFAULT                 0x0000
#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT                 0x0000
#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT               0x0000
#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT                 0x0002
#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT             0x8081020
#define mmCP_MEC1_F32_INT_DIS_DEFAULT                   0x0000
#define mmCP_MEC1_INSTR_PNTR_DEFAULT                    0x0000
#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT            0x0002
#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT              0x0000
#define mmCP_MEC2_F32_INT_DIS_DEFAULT                   0x0000
#define mmCP_MEC2_INSTR_PNTR_DEFAULT                    0x0000
#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT            0x0002
#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT              0x0000
#define mmCP_MEC_CNTL_DEFAULT                           0x50000000
#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT           0x0048
#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT           0xFFFFFFC
#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT                0xCDCDCDCD
#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT                 0xCDCDCDCD
#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT                0xCDCDCDCD
#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT                 0xCDCDCDCD
#define mmCP_MEM_SLP_CNTL_DEFAULT                       0x20200
#define mmCP_MEQ_AVAIL_DEFAULT                          0x01CD
#define mmCP_MEQ_STAT_DEFAULT                           0x1CD01CD
#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT                  0x0010
#define mmCP_MEQ_THRESHOLDS_DEFAULT                     0x8040
#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT                 0xCDCDCDCD
#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT                 0xCDCDCDCD
#define mmCP_ME_CNTL_DEFAULT                            0x15000000
#define mmCP_ME_COHER_BASE_DEFAULT                      0x0000
#define mmCP_ME_COHER_BASE_HI_DEFAULT                   0x0000
#define mmCP_ME_COHER_CNTL_DEFAULT                      0x0000
#define mmCP_ME_COHER_SIZE_DEFAULT                      0x0000
#define mmCP_ME_COHER_SIZE_HI_DEFAULT                   0x0000
#define mmCP_ME_COHER_STATUS_DEFAULT                    0x0000
#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT            0xCDCDCDCD
#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT            0xCDCDCDCD
#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT            0xCDCDCDCD
#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT            0xCDCDCDCD
#define mmCP_ME_HEADER_DUMP_DEFAULT                     0xCDCDCDCD
#define mmCP_ME_INSTR_PNTR_DEFAULT                      0x0000
#define mmCP_ME_INTR_ROUTINE_START_DEFAULT              0x0002
#define mmCP_ME_MC_RADDR_LO_DEFAULT                     0xCDCDCDCC
#define mmCP_ME_MC_WADDR_LO_DEFAULT                     0xCDCDCDCC
#define mmCP_ME_MC_WDATA_HI_DEFAULT                     0xCDCDCDCD
#define mmCP_ME_MC_WDATA_LO_DEFAULT                     0xCDCDCDCD
#define mmCP_ME_PREEMPTION_DEFAULT                      0x0000
#define mmCP_ME_PRGRM_CNTR_START_DEFAULT                0x0000
#define mmCP_ME_RAM_DATA_DEFAULT                        0xCDCDCDCD
#define mmCP_ME_RAM_RADDR_DEFAULT                       0x0000
#define mmCP_ME_RAM_WADDR_DEFAULT                       0x0000
#define mmCP_MQD_BASE_ADDR_DEFAULT                      0x0000
#define mmCP_MQD_BASE_ADDR_HI_DEFAULT                   0x0000
#define mmCP_MQD_CONTROL_DEFAULT                        0x0100
#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT          0x0000
#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT          0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT         0x0000
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT         0x0000
#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT                 0x0000
#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT                 0x0000
#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT                  0x0000
#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT                  0x0000
#define mmCP_PERFMON_CNTL_DEFAULT                       0x0000
#define mmCP_PERFMON_CNTX_CNTL_DEFAULT                  0x0000
#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT                0xCDCDCDCD
#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT                0xCDCDCDCD
#define mmCP_PFP_COMPLETION_STATUS_DEFAULT              0x0000
#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT           0xCDCDCDCD
#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT           0xCDCDCDCD
#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT           0xCDCDCDCD
#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT           0xCDCDCDCD
#define mmCP_PFP_HEADER_DUMP_DEFAULT                    0xCDCDCDCD
#define mmCP_PFP_IB_CONTROL_DEFAULT                     0x0000
#define mmCP_PFP_INSTR_PNTR_DEFAULT                     0x0000
#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT             0x0002
#define mmCP_PFP_LOAD_CONTROL_DEFAULT                   0x0000
#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT             0x0000
#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT          0x0000
#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT               0x0000
#define mmCP_PFP_UCODE_ADDR_DEFAULT                     0x0000
#define mmCP_PFP_UCODE_DATA_DEFAULT                     0xCDCDCDCD
#define mmCP_PIPEID_DEFAULT                             0x0000
#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT                 0x0000
#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT                 0x0000
#define mmCP_PIPE_STATS_CONTROL_DEFAULT                 0x0000
#define mmCP_PQ_STATUS_DEFAULT                          0x0000
#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT                 0x0000
#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT                  0x40000001
#define mmCP_PRED_NOT_VISIBLE_DEFAULT                   0x0000
#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT                0x0000
#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT                0x0000
#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT                0x0000
#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT                0x0000
#define mmCP_PWR_CNTL_DEFAULT                           0x0000
#define mmCP_QUEUE_THRESHOLDS_DEFAULT                   0x2B16
#define mmCP_RB0_BASE_DEFAULT                           0xCDCDCDCD
#define mmCP_RB0_BASE_HI_DEFAULT                        0x00CD
#define mmCP_RB0_BUFSZ_MASK_DEFAULT                     0x0000
#define mmCP_RB0_RPTR_ADDR_DEFAULT                      0x0000
#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT                   0x0000
#define mmCP_RB0_RPTR_DEFAULT                           0xDCDCD
#define mmCP_RB0_WPTR_DEFAULT                           0x0000
#define mmCP_RB0_WPTR_HI_DEFAULT                        0x0000
#define mmCP_RB1_BASE_DEFAULT                           0xCDCDCDCD
#define mmCP_RB1_BASE_HI_DEFAULT                        0x00CD
#define mmCP_RB1_RPTR_ADDR_DEFAULT                      0x0000
#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT                   0x0000
#define mmCP_RB1_RPTR_DEFAULT                           0xDCDCD
#define mmCP_RB1_WPTR_DEFAULT                           0x0000
#define mmCP_RB1_WPTR_HI_DEFAULT                        0x0000
#define mmCP_RB2_BASE_DEFAULT                           0xCDCDCDCD
#define mmCP_RB2_RPTR_ADDR_DEFAULT                      0x0000
#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT                   0x0000
#define mmCP_RB2_RPTR_DEFAULT                           0xDCDCD
#define mmCP_RB2_WPTR_DEFAULT                           0x0000
#define mmCP_RB_BASE_DEFAULT                            0xCDCDCDCD
#define mmCP_RB_BUFSZ_MASK_DEFAULT                      0x0000
#define mmCP_RB_DOORBELL_CLEAR_DEFAULT                  0x0000
#define mmCP_RB_DOORBELL_CONTROL_DEFAULT                0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT__GFX09   0x0000
#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT            0x0000
#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT            0x0044
#define mmCP_RB_OFFSET_DEFAULT                          0xDCDCD
#define mmCP_RB_RPTR_ADDR_DEFAULT                       0x0000
#define mmCP_RB_RPTR_ADDR_HI_DEFAULT                    0x0000
#define mmCP_RB_RPTR_DEFAULT                            0xDCDCD
#define mmCP_RB_RPTR_WR_DEFAULT                         0x0000
#define mmCP_RB_STATUS_DEFAULT                          0x0000
#define mmCP_RB_VMID_DEFAULT                            0x0000
#define mmCP_RB_WPTR_DEFAULT                            0x0000
#define mmCP_RB_WPTR_DELAY_DEFAULT                      0x0000
#define mmCP_RB_WPTR_HI_DEFAULT                         0x0000
#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT               0x0000
#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT               0x0000
#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT                  0x400100
#define mmCP_RING0_PRIORITY_DEFAULT                     0x0002
#define mmCP_RING1_PRIORITY_DEFAULT                     0x0002
#define mmCP_RING2_PRIORITY_DEFAULT                     0x0002
#define mmCP_RINGID_DEFAULT                             0x0000
#define mmCP_RING_PRIORITY_CNTS_DEFAULT                 0x8081020
#define mmCP_ROQ_THRESHOLDS_DEFAULT                     0x3010
#define mmCP_SAMPLE_STATUS_DEFAULT                      0x0000
#define mmCP_SCRATCH_DATA_DEFAULT                       0xCDCDCDCD
#define mmCP_SCRATCH_INDEX_DEFAULT                      0x0000
#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT               0x0000
#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT               0x0000
#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT               0x0000
#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT               0x0000
#define mmCP_SEM_WAIT_TIMER_DEFAULT                     0x0000
#define mmCP_SIG_SEM_ADDR_HI_DEFAULT                    0xC101CDCD
#define mmCP_SIG_SEM_ADDR_LO_DEFAULT                    0xCDCDCDC9
#define mmCP_SOFT_RESET_CNTL_DEFAULT                    0x0000
#define mmCP_STALLED_STAT1_DEFAULT                      0xD80CC05
#define mmCP_STALLED_STAT3_DEFAULT                      0xDCCCD
#define mmCP_STQ_AVAIL_DEFAULT                          0x01CD
#define mmCP_STQ_STAT_DEFAULT                           0x01CD
#define mmCP_STQ_THRESHOLDS_DEFAULT                     0x804000
#define mmCP_STQ_WR_STAT_DEFAULT                        0x01CD
#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT                 0x0000
#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT                 0x0000
#define mmCP_STREAM_OUT_CONTROL_DEFAULT                 0x0000
#define mmCP_STRMOUT_CNTL_DEFAULT                       0x0000
#define mmCP_ST_BASE_HI_DEFAULT                         0xCDCD
#define mmCP_ST_BASE_LO_DEFAULT                         0xCDCDCDCC
#define mmCP_ST_BUFSZ_DEFAULT                           0x0000
#define mmCP_ST_CMD_BUFSZ_DEFAULT                       0x0000
#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT               0x0000
#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT               0x0000
#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT               0x0000
#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT               0x0000
#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT               0x0000
#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT               0x0000
#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT                0x0000
#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT                0x0000
#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT               0x0000
#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT               0x0000
#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT                0x0000
#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT                0x0000
#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT                0x0000
#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT                0x0000
#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT               0x0000
#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT               0x0000
#define mmCP_VIRT_STATUS_DEFAULT                        0x0000
#define mmCP_VMID_DEFAULT                               0x0000
#define mmCP_VMID_PREEMPT_DEFAULT                       0x0000
#define mmCP_VMID_RESET_DEFAULT                         0x0000
#define mmCP_VMID_STATUS_DEFAULT                        0x0000
#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT               0x0000
#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT                   0xC101CDCD
#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT                   0xCDCDCDC9
#define mmCS_COPY_STATE_DEFAULT                         0x0005
#define mmDB_ALPHA_TO_MASK_DEFAULT                      0x1CD01
#define mmDB_CGTT_CLK_CTRL_0_DEFAULT                    0x0100
#define mmDB_COUNT_CONTROL_DEFAULT                      0x0001
#define mmDB_CREDIT_LIMIT_DEFAULT                       0x0000
#define mmDB_DEBUG_DEFAULT                              0x0000
#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT                   0xCDCDCDCD
#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT                   0xCDCDCDCD
#define mmDB_DEPTH_CLEAR_DEFAULT                        0xCDCDCDCD
#define mmDB_DEPTH_CONTROL_DEFAULT                      0xC04005CD
#define mmDB_DFSM_CONTROL_DEFAULT                       0x000D
#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT               0xCDCDCDCD
#define mmDB_DFSM_WATCHDOG_DEFAULT                      0xF4240
#define mmDB_DFSM_WATERMARK_DEFAULT__GFX09              0x640064
#define mmDB_EXCEPTION_CONTROL_DEFAULT                  0x0000
#define mmDB_FIFO_DEPTH1_DEFAULT                        0x0000
#define mmDB_FIFO_DEPTH2_DEFAULT                        0x0000
#define mmDB_FREE_CACHELINES_DEFAULT                    0x0000
#define mmDB_HTILE_DATA_BASE_DEFAULT                    0xCDCDCDCD
#define mmDB_HTILE_DATA_BASE_HI_DEFAULT                 0x00CD
#define mmDB_MEM_ARB_WATERMARKS_DEFAULT                 0x4040404
#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT                0x4DCDCDCD
#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT               0xCDCDCDCD
#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT                0x4DCDCDCD
#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT               0xCDCDCDCD
#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT                0x4DCDCDCD
#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT               0xCDCDCDCD
#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT                0x4DCDCDCD
#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT               0xCDCDCDCD
#define mmDB_PERFCOUNTER0_HI_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER0_LO_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT               0xCD0DCDCD
#define mmDB_PERFCOUNTER0_SELECT_DEFAULT                0xCD0DCDCD
#define mmDB_PERFCOUNTER1_HI_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER1_LO_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT               0xCD0DCDCD
#define mmDB_PERFCOUNTER1_SELECT_DEFAULT                0xCD0DCDCD
#define mmDB_PERFCOUNTER2_HI_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER2_LO_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER2_SELECT_DEFAULT                0xCD0DCDCD
#define mmDB_PERFCOUNTER3_HI_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER3_LO_DEFAULT                    0xCDCDCDCD
#define mmDB_PERFCOUNTER3_SELECT_DEFAULT                0xCD0DCDCD
#define mmDB_PRELOAD_CONTROL_DEFAULT                    0xCDCDCDCD
#define mmDB_RENDER_CONTROL_DEFAULT                     0x0DCD
#define mmDB_RENDER_OVERRIDE_DEFAULT                    0xC80DCDCD
#define mmDB_RING_CONTROL_DEFAULT                       0x0001
#define mmDB_RMI_CACHE_POLICY_DEFAULT__GFX09            0xF0F0F07
#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT            0x10DCDC5
#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT            0x10DCDC5
#define mmDB_STENCILREFMASK_BF_DEFAULT                  0xCDCDCDCD
#define mmDB_STENCILREFMASK_DEFAULT                     0xCDCDCDCD
#define mmDB_STENCIL_CLEAR_DEFAULT                      0x00CD
#define mmDB_STENCIL_CONTROL_DEFAULT                    0xCDCDCD
#define mmDB_STENCIL_INFO2_DEFAULT__GFX09               0x0000
#define mmDB_STENCIL_READ_BASE_DEFAULT                  0xCDCDCDCD
#define mmDB_STENCIL_READ_BASE_HI_DEFAULT               0x00CD
#define mmDB_STENCIL_WRITE_BASE_DEFAULT                 0xCDCDCDCD
#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT              0x00CD
#define mmDB_SUBTILE_CONTROL_DEFAULT                    0x0000
#define mmDB_ZPASS_COUNT_HI_DEFAULT                     0x4DCDCDCD
#define mmDB_ZPASS_COUNT_LOW_DEFAULT                    0xCDCDCDCD
#define mmDB_Z_INFO2_DEFAULT__GFX09                     0x0000
#define mmDB_Z_READ_BASE_DEFAULT                        0xCDCDCDCD
#define mmDB_Z_READ_BASE_HI_DEFAULT                     0x00CD
#define mmDB_Z_WRITE_BASE_DEFAULT                       0xCDCDCDCD
#define mmDB_Z_WRITE_BASE_HI_DEFAULT                    0x00CD
#define mmDIDT_IND_DATA_DEFAULT                         0xCDCDCDCD
#define mmDIDT_IND_INDEX_DEFAULT                        0xCDCDCDCD
#define mmGB_EDC_MODE_DEFAULT                           0x0000
#define mmGB_GPU_ID_DEFAULT                             0x0000
#define mmGB_MACROTILE_MODE14_DEFAULT                   0x0000
#define mmGB_MACROTILE_MODE15_DEFAULT                   0x0000
#define mmGB_MACROTILE_MODE7_DEFAULT                    0x0000
#define mmGB_TILE_MODE0_DEFAULT                         0x0000
#define mmGB_TILE_MODE10_DEFAULT                        0x0000
#define mmGB_TILE_MODE11_DEFAULT                        0x0000
#define mmGB_TILE_MODE12_DEFAULT                        0x0000
#define mmGB_TILE_MODE13_DEFAULT                        0x0000
#define mmGB_TILE_MODE14_DEFAULT                        0x0000
#define mmGB_TILE_MODE15_DEFAULT                        0x0000
#define mmGB_TILE_MODE16_DEFAULT                        0x0000
#define mmGB_TILE_MODE17_DEFAULT                        0x0000
#define mmGB_TILE_MODE18_DEFAULT                        0x0000
#define mmGB_TILE_MODE19_DEFAULT                        0x0000
#define mmGB_TILE_MODE1_DEFAULT                         0x0000
#define mmGB_TILE_MODE20_DEFAULT                        0x0000
#define mmGB_TILE_MODE21_DEFAULT                        0x0000
#define mmGB_TILE_MODE22_DEFAULT                        0x0000
#define mmGB_TILE_MODE23_DEFAULT                        0x0000
#define mmGB_TILE_MODE24_DEFAULT                        0x0000
#define mmGB_TILE_MODE25_DEFAULT                        0x0000
#define mmGB_TILE_MODE26_DEFAULT                        0x0000
#define mmGB_TILE_MODE27_DEFAULT                        0x0000
#define mmGB_TILE_MODE28_DEFAULT                        0x0000
#define mmGB_TILE_MODE29_DEFAULT                        0x0000
#define mmGB_TILE_MODE2_DEFAULT                         0x0000
#define mmGB_TILE_MODE30_DEFAULT                        0x0000
#define mmGB_TILE_MODE31_DEFAULT                        0x0000
#define mmGB_TILE_MODE3_DEFAULT                         0x0000
#define mmGB_TILE_MODE4_DEFAULT                         0x0000
#define mmGB_TILE_MODE5_DEFAULT                         0x0000
#define mmGB_TILE_MODE6_DEFAULT                         0x0000
#define mmGB_TILE_MODE7_DEFAULT                         0x0000
#define mmGB_TILE_MODE8_DEFAULT                         0x0000
#define mmGB_TILE_MODE9_DEFAULT                         0x0000
#define mmGCEA_CGTT_CLK_CTRL_DEFAULT                    0x0100
#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT                 0x0000
#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT                 0x0000
#define mmGCEA_PERFCOUNTER_HI_DEFAULT                   0x0000
#define mmGCEA_PERFCOUNTER_LO_DEFAULT                   0x0000
#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT            0x4000000
#define mmGC_CAC_AGGR_LOWER_DEFAULT                     0x0000
#define mmGC_CAC_AGGR_UPPER_DEFAULT                     0x0000
#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT                  0x0100
#define mmGC_CAC_CTRL_2_DEFAULT                         0x0000
#define mmGC_CAC_IND_DATA_DEFAULT                       0x0000
#define mmGC_CAC_IND_INDEX_DEFAULT                      0x0000
#define mmGC_CAC_SOFT_CTRL_DEFAULT                      0x0000
#define mmGC_DIDT_CTRL0_DEFAULT                         0x0000
#define mmGC_DIDT_CTRL1_DEFAULT                         0xFFFF0000
#define mmGC_DIDT_CTRL2_DEFAULT                         0x1880000F
#define mmGC_DIDT_DROOP_CTRL_DEFAULT__GFX09             0x0000
#define mmGC_DIDT_WEIGHT_1_DEFAULT__GFX09               0x0000
#define mmGC_DIDT_WEIGHT_DEFAULT                        0x0000
#define mmGC_EDC_DROOP_CTRL_DEFAULT__GFX09              0x100000
#define mmGC_EDC_OVERFLOW_DEFAULT                       0x0000
#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT            0x0000
#define mmGC_EDC_STATUS_DEFAULT                         0x0000
#define mmGC_EDC_THRESHOLD_DEFAULT                      0x0000
#define mmGC_PRIV_MODE_DEFAULT                          0x0000
#define mmGC_USER_PRIM_CONFIG_DEFAULT                   0x0000
#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT            0x0000
#define mmGC_USER_RB_REDUNDANCY_DEFAULT                 0x0000
#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT           0x0000
#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT            0x0000
#define mmGDS_ATOM_BASE_DEFAULT                         0x0000
#define mmGDS_ATOM_CNTL_DEFAULT                         0x0000
#define mmGDS_ATOM_COMPLETE_DEFAULT                     0x0001
#define mmGDS_ATOM_DST_DEFAULT                          0x0000
#define mmGDS_ATOM_OFFSET0_DEFAULT                      0x0000
#define mmGDS_ATOM_OFFSET1_DEFAULT                      0x0000
#define mmGDS_ATOM_OP_DEFAULT                           0x0000
#define mmGDS_ATOM_READ0_DEFAULT                        0x0000
#define mmGDS_ATOM_READ0_U_DEFAULT                      0x0000
#define mmGDS_ATOM_READ1_DEFAULT                        0x0000
#define mmGDS_ATOM_READ1_U_DEFAULT                      0x0000
#define mmGDS_ATOM_SIZE_DEFAULT                         0x0000
#define mmGDS_ATOM_SRC0_DEFAULT                         0x0000
#define mmGDS_ATOM_SRC0_U_DEFAULT                       0x0000
#define mmGDS_ATOM_SRC1_DEFAULT                         0x0000
#define mmGDS_ATOM_SRC1_U_DEFAULT                       0x0000
#define mmGDS_CNTL_STATUS_DEFAULT                       0x4DCD
#define mmGDS_CONFIG_DEFAULT                            0x0000
#define mmGDS_CS_CTXSW_CNT0_DEFAULT                     0x0000
#define mmGDS_CS_CTXSW_CNT1_DEFAULT                     0x0000
#define mmGDS_CS_CTXSW_CNT2_DEFAULT                     0x0000
#define mmGDS_CS_CTXSW_CNT3_DEFAULT                     0x0000
#define mmGDS_CS_CTXSW_STATUS_DEFAULT                   0x0000
#define mmGDS_DSM_CNTL2_DEFAULT                         0x0000
#define mmGDS_DSM_CNTL_DEFAULT                          0x0000
#define mmGDS_EDC_CNT_DEFAULT                           0x0000
#define mmGDS_EDC_GRBM_CNT_DEFAULT                      0x0000
#define mmGDS_EDC_OA_DED_DEFAULT                        0x0000
#define mmGDS_EDC_OA_PHY_CNT_DEFAULT                    0x0000
#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT                   0x0000
#define mmGDS_ENHANCE2_DEFAULT                          0x0000
#define mmGDS_ENHANCE_DEFAULT                           0x0000
#define mmGDS_GFX_CTXSW_STATUS_DEFAULT                  0x0000
#define mmGDS_GS_CTXSW_CNT0_DEFAULT                     0x0000
#define mmGDS_GS_CTXSW_CNT1_DEFAULT                     0x0000
#define mmGDS_GS_CTXSW_CNT2_DEFAULT                     0x0000
#define mmGDS_GS_CTXSW_CNT3_DEFAULT                     0x0000
#define mmGDS_GWS_RESET0_DEFAULT                        0x0000
#define mmGDS_GWS_RESET1_DEFAULT                        0x0000
#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT                 0x0000
#define mmGDS_GWS_RESOURCE_CNT_DEFAULT                  0x0000
#define mmGDS_GWS_RESOURCE_DEFAULT                      0x0000
#define mmGDS_GWS_RESOURCE_RESET_DEFAULT                0x0000
#define mmGDS_GWS_VMID0_DEFAULT                         0x400000
#define mmGDS_GWS_VMID10_DEFAULT                        0x400000
#define mmGDS_GWS_VMID11_DEFAULT                        0x400000
#define mmGDS_GWS_VMID12_DEFAULT                        0x400000
#define mmGDS_GWS_VMID13_DEFAULT                        0x400000
#define mmGDS_GWS_VMID14_DEFAULT                        0x400000
#define mmGDS_GWS_VMID15_DEFAULT                        0x400000
#define mmGDS_GWS_VMID1_DEFAULT                         0x400000
#define mmGDS_GWS_VMID2_DEFAULT                         0x400000
#define mmGDS_GWS_VMID3_DEFAULT                         0x400000
#define mmGDS_GWS_VMID4_DEFAULT                         0x400000
#define mmGDS_GWS_VMID5_DEFAULT                         0x400000
#define mmGDS_GWS_VMID6_DEFAULT                         0x400000
#define mmGDS_GWS_VMID7_DEFAULT                         0x400000
#define mmGDS_GWS_VMID8_DEFAULT                         0x400000
#define mmGDS_GWS_VMID9_DEFAULT                         0x400000
#define mmGDS_OA_ADDRESS_DEFAULT                        0x0000
#define mmGDS_OA_CGPG_RESTORE_DEFAULT                   0x0000
#define mmGDS_OA_CNTL_DEFAULT                           0x0000
#define mmGDS_OA_COUNTER_DEFAULT                        0x0000
#define mmGDS_OA_INCDEC_DEFAULT                         0x0000
#define mmGDS_OA_RESET_DEFAULT                          0x0000
#define mmGDS_OA_RESET_MASK_DEFAULT                     0x0000
#define mmGDS_OA_RING_SIZE_DEFAULT                      0x0000
#define mmGDS_OA_VMID0_DEFAULT                          0x0000
#define mmGDS_OA_VMID10_DEFAULT                         0x0000
#define mmGDS_OA_VMID11_DEFAULT                         0x0000
#define mmGDS_OA_VMID12_DEFAULT                         0x0000
#define mmGDS_OA_VMID13_DEFAULT                         0x0000
#define mmGDS_OA_VMID14_DEFAULT                         0x0000
#define mmGDS_OA_VMID15_DEFAULT                         0x0000
#define mmGDS_OA_VMID1_DEFAULT                          0x0000
#define mmGDS_OA_VMID2_DEFAULT                          0x0000
#define mmGDS_OA_VMID3_DEFAULT                          0x0000
#define mmGDS_OA_VMID4_DEFAULT                          0x0000
#define mmGDS_OA_VMID5_DEFAULT                          0x0000
#define mmGDS_OA_VMID6_DEFAULT                          0x0000
#define mmGDS_OA_VMID7_DEFAULT                          0x0000
#define mmGDS_OA_VMID8_DEFAULT                          0x0000
#define mmGDS_OA_VMID9_DEFAULT                          0x0000
#define mmGDS_PERFCOUNTER0_HI_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER0_LO_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER1_HI_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER1_LO_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER2_HI_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER2_LO_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER3_HI_DEFAULT                   0xCDCDCDCD
#define mmGDS_PERFCOUNTER3_LO_DEFAULT                   0xCDCDCDCD
#define mmGDS_PROTECTION_FAULT_DEFAULT                  0x0000
#define mmGDS_PS0_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS0_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS0_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS0_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS1_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS1_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS1_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS1_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS2_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS2_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS2_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS2_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS3_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS3_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS3_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS3_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS4_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS4_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS4_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS4_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS5_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS5_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS5_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS5_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS6_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS6_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS6_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS6_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_PS7_CTXSW_CNT0_DEFAULT__GFX09             0x0000
#define mmGDS_PS7_CTXSW_CNT1_DEFAULT__GFX09             0x0000
#define mmGDS_PS7_CTXSW_CNT2_DEFAULT__GFX09             0x0000
#define mmGDS_PS7_CTXSW_CNT3_DEFAULT__GFX09             0x0000
#define mmGDS_RD_ADDR_DEFAULT                           0x0000
#define mmGDS_RD_BURST_ADDR_DEFAULT                     0x0000
#define mmGDS_RD_BURST_COUNT_DEFAULT                    0x0000
#define mmGDS_RD_BURST_DATA_DEFAULT                     0x0000
#define mmGDS_RD_DATA_DEFAULT                           0x0000
#define mmGDS_VMID0_BASE_DEFAULT                        0x0000
#define mmGDS_VMID0_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID10_BASE_DEFAULT                       0x0000
#define mmGDS_VMID10_SIZE_DEFAULT                       0x10000
#define mmGDS_VMID11_BASE_DEFAULT                       0x0000
#define mmGDS_VMID11_SIZE_DEFAULT                       0x10000
#define mmGDS_VMID12_BASE_DEFAULT                       0x0000
#define mmGDS_VMID12_SIZE_DEFAULT                       0x10000
#define mmGDS_VMID13_BASE_DEFAULT                       0x0000
#define mmGDS_VMID13_SIZE_DEFAULT                       0x10000
#define mmGDS_VMID14_BASE_DEFAULT                       0x0000
#define mmGDS_VMID14_SIZE_DEFAULT                       0x10000
#define mmGDS_VMID15_BASE_DEFAULT                       0x0000
#define mmGDS_VMID15_SIZE_DEFAULT                       0x10000
#define mmGDS_VMID1_BASE_DEFAULT                        0x0000
#define mmGDS_VMID1_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID2_BASE_DEFAULT                        0x0000
#define mmGDS_VMID2_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID3_BASE_DEFAULT                        0x0000
#define mmGDS_VMID3_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID4_BASE_DEFAULT                        0x0000
#define mmGDS_VMID4_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID5_BASE_DEFAULT                        0x0000
#define mmGDS_VMID5_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID6_BASE_DEFAULT                        0x0000
#define mmGDS_VMID6_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID7_BASE_DEFAULT                        0x0000
#define mmGDS_VMID7_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID8_BASE_DEFAULT                        0x0000
#define mmGDS_VMID8_SIZE_DEFAULT                        0x10000
#define mmGDS_VMID9_BASE_DEFAULT                        0x0000
#define mmGDS_VMID9_SIZE_DEFAULT                        0x10000
#define mmGDS_VM_PROTECTION_FAULT_DEFAULT               0x0000
#define mmGDS_VS_CTXSW_CNT0_DEFAULT                     0x0000
#define mmGDS_VS_CTXSW_CNT1_DEFAULT                     0x0000
#define mmGDS_VS_CTXSW_CNT2_DEFAULT                     0x0000
#define mmGDS_VS_CTXSW_CNT3_DEFAULT                     0x0000
#define mmGDS_WD_GDS_CSB_DEFAULT                        0x0000
#define mmGDS_WRITE_COMPLETE_DEFAULT                    0x0000
#define mmGDS_WR_ADDR_DEFAULT                           0x0000
#define mmGDS_WR_BURST_ADDR_DEFAULT                     0x0000
#define mmGDS_WR_BURST_DATA_DEFAULT                     0x0000
#define mmGDS_WR_DATA_DEFAULT                           0x0000
#define mmGFX_COPY_STATE_DEFAULT                        0x0005
#define mmGFX_PIPE_CONTROL_DEFAULT                      0x0000
#define mmGRBM_CAM_DATA_DEFAULT                         0x0000
#define mmGRBM_CAM_INDEX_DEFAULT                        0x0000
#define mmGRBM_CGTT_CLK_CNTL_DEFAULT                    0x0100
#define mmGRBM_CHICKEN_BITS_DEFAULT                     0x0000
#define mmGRBM_CHIP_REVISION_DEFAULT                    0x0000
#define mmGRBM_CNTL_DEFAULT                             0x0018
#define mmGRBM_DSM_BYPASS_DEFAULT                       0x0000
#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT                   0x1008
#define mmGRBM_GFX_CNTL_DEFAULT                         0x0000
#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT                 0x0000
#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT               0x0000
#define mmGRBM_GFX_INDEX_DEFAULT                        0xE0000000
#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT                0xE0000000
#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT              0x0000
#define mmGRBM_HYP_CAM_DATA_DEFAULT                     0x0000
#define mmGRBM_HYP_CAM_INDEX_DEFAULT                    0x0000
#define mmGRBM_IH_CREDIT_DEFAULT                        0x10000
#define mmGRBM_INT_CNTL_DEFAULT                         0x0000
#define mmGRBM_IOV_ERROR_DEFAULT                        0x0000
#define mmGRBM_NOWHERE_DEFAULT                          0x0000
#define mmGRBM_PERFCOUNTER0_HI_DEFAULT                  0x0000
#define mmGRBM_PERFCOUNTER0_LO_DEFAULT                  0x0000
#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT              0x0000
#define mmGRBM_PERFCOUNTER1_HI_DEFAULT                  0x0000
#define mmGRBM_PERFCOUNTER1_LO_DEFAULT                  0x0000
#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT              0x0000
#define mmGRBM_PWR_CNTL2_DEFAULT                        0x10000
#define mmGRBM_PWR_CNTL_DEFAULT                         0x0000
#define mmGRBM_READ_ERROR2_DEFAULT                      0x0000
#define mmGRBM_READ_ERROR_DEFAULT                       0x0000
#define mmGRBM_RSMU_CFG_DEFAULT                         0x11000
#define mmGRBM_RSMU_READ_ERROR_DEFAULT                  0x0000
#define mmGRBM_SCRATCH_REG0_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG1_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG2_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG3_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG4_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG5_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG6_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SCRATCH_REG7_DEFAULT                     0xCDCDCDCD
#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT               0x0000
#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT               0x0000
#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT           0x0000
#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT               0x0000
#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT               0x0000
#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT           0x0000
#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT               0x0000
#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT               0x0000
#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT           0x0000
#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT               0x0000
#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT               0x0000
#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT           0x0000
#define mmGRBM_SKEW_CNTL_DEFAULT                        0x0020
#define mmGRBM_SOFT_RESET_DEFAULT                       0x0000
#define mmGRBM_TRAP_ADDR_DEFAULT                        0x0000
#define mmGRBM_TRAP_ADDR_MSK_DEFAULT                    0x3FFFF
#define mmGRBM_TRAP_OP_DEFAULT                          0x0000
#define mmGRBM_TRAP_WD_DEFAULT                          0x0000
#define mmGRBM_TRAP_WD_MSK_DEFAULT                      0xFFFFFFFF
#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT            0x28EA
#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT          0x2891
#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT                 0x0030
#define mmGRBM_WRITE_ERROR_DEFAULT                      0x0000
#define mmIA_CNTL_STATUS_DEFAULT__GFX09                 0x000D
#define mmIA_ENHANCE_DEFAULT                            0xCDCDCDCD
#define mmIA_PERFCOUNTER0_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER0_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT__GFX09        0xDCDCD
#define mmIA_PERFCOUNTER0_SELECT_DEFAULT__GFX09         0xDCDCD
#define mmIA_PERFCOUNTER1_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER1_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER1_SELECT_DEFAULT__GFX09         0x00CD
#define mmIA_PERFCOUNTER2_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER2_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER2_SELECT_DEFAULT__GFX09         0x00CD
#define mmIA_PERFCOUNTER3_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER3_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmIA_PERFCOUNTER3_SELECT_DEFAULT__GFX09         0x00CD
#define mmIA_UTCL1_CNTL_DEFAULT                         0x0080
#define mmIA_UTCL1_STATUS_DEFAULT                       0x0000
#define mmIH_ACTIVE_FCN_ID_DEFAULT                      0x0000
#define mmIH_CHICKEN_DEFAULT                            0x0000
#define mmIH_CID_REMAP_DATA_DEFAULT                     0x0000
#define mmIH_CID_REMAP_INDEX_DEFAULT                    0x0000
#define mmIH_CLIENT_CFG_DATA_DEFAULT                    0x0000
#define mmIH_CLIENT_CFG_DEFAULT                         0x001F
#define mmIH_CLIENT_CFG_INDEX_DEFAULT                   0x0000
#define mmIH_CLIENT_CREDIT_ERROR_DEFAULT                0x0000
#define mmIH_CLK_CTRL_DEFAULT                           0x0000
#define mmIH_CNTL_DEFAULT                               0x1000000
#define mmIH_COOKIE_0_DEFAULT                           0x0000
#define mmIH_COOKIE_1_DEFAULT                           0x0000
#define mmIH_COOKIE_2_DEFAULT                           0x0000
#define mmIH_COOKIE_3_DEFAULT                           0x0000
#define mmIH_COOKIE_4_DEFAULT                           0x0000
#define mmIH_COOKIE_5_DEFAULT                           0x0000
#define mmIH_COOKIE_6_DEFAULT                           0x0000
#define mmIH_COOKIE_7_DEFAULT                           0x0000
#define mmIH_COOKIE_REC_VIOLATION_LOG_DEFAULT           0x0000
#define mmIH_CREDIT_STATUS_DEFAULT                      0xFFFFFFFE
#define mmIH_DOORBELL_RPTR_DEFAULT                      0x0000
#define mmIH_DOORBELL_RPTR_RING1_DEFAULT                0x0000
#define mmIH_DOORBELL_RPTR_RING2_DEFAULT                0x0000
#define mmIH_DSM_MATCH_DATA_CONTROL_DEFAULT             0xFFFFFFF
#define mmIH_DSM_MATCH_FCN_ID_DEFAULT                   0x0000
#define mmIH_DSM_MATCH_FIELD_CONTROL_DEFAULT            0x007F
#define mmIH_DSM_MATCH_VALUE_BIT_31_0_DEFAULT           0x0000
#define mmIH_DSM_MATCH_VALUE_BIT_63_32_DEFAULT          0x0000
#define mmIH_DSM_MATCH_VALUE_BIT_95_64_DEFAULT          0x0000
#define mmIH_GPU_IOV_VIOLATION_LOG_DEFAULT              0x0000
#define mmIH_INT_FLAGS_DEFAULT                          0x0000
#define mmIH_INT_FLOOD_CNTL_DEFAULT                     0x0000
#define mmIH_INT_FLOOD_STATUS_DEFAULT                   0x0000
#define mmIH_LAST_INT_INFO0_DEFAULT                     0x0000
#define mmIH_LAST_INT_INFO1_DEFAULT                     0x0000
#define mmIH_LAST_INT_INFO2_DEFAULT                     0x0000
#define mmIH_LIMIT_INT_RATE_CNTL_DEFAULT                0x0000
#define mmIH_MMHUB_ERROR_DEFAULT                        0x0000
#define mmIH_PERFCOUNTER0_RESULT_DEFAULT                0x0000
#define mmIH_PERFCOUNTER1_RESULT_DEFAULT                0x0000
#define mmIH_PERFMON_CNTL_DEFAULT                       0x0000
#define mmIH_RB0_INT_FLOOD_STATUS_DEFAULT               0x0000
#define mmIH_RB1_INT_FLOOD_STATUS_DEFAULT               0x0000
#define mmIH_RB2_INT_FLOOD_STATUS_DEFAULT               0x0000
#define mmIH_RB_BASE_DEFAULT                            0x0000
#define mmIH_RB_BASE_HI_DEFAULT                         0x0000
#define mmIH_RB_BASE_HI_RING1_DEFAULT                   0x0000
#define mmIH_RB_BASE_HI_RING2_DEFAULT                   0x0000
#define mmIH_RB_BASE_RING1_DEFAULT                      0x0000
#define mmIH_RB_BASE_RING2_DEFAULT                      0x0000
#define mmIH_RB_CNTL_DEFAULT                            0x10610000
#define mmIH_RB_CNTL_RING1_DEFAULT                      0x10410000
#define mmIH_RB_CNTL_RING2_DEFAULT                      0x10410000
#define mmIH_RB_RPTR_DEFAULT                            0x0000
#define mmIH_RB_RPTR_RING1_DEFAULT                      0x0000
#define mmIH_RB_RPTR_RING2_DEFAULT                      0x0000
#define mmIH_RB_WPTR_ADDR_HI_DEFAULT                    0x0000
#define mmIH_RB_WPTR_ADDR_LO_DEFAULT                    0x0000
#define mmIH_RB_WPTR_DEFAULT                            0x0000
#define mmIH_RB_WPTR_RING1_DEFAULT                      0x0000
#define mmIH_RB_WPTR_RING2_DEFAULT                      0x0000
#define mmIH_REGISTER_LAST_PART0_DEFAULT                0x0000
#define mmIH_REGISTER_LAST_PART1_DEFAULT                0x0000
#define mmIH_REGISTER_LAST_PART2_DEFAULT                0x0000
#define mmIH_SCRATCH_DEFAULT                            0x0000
#define mmIH_STORM_CLIENT_LIST_CNTL_DEFAULT             0x0000
#define mmIH_VERSION_DEFAULT                            0x0400
#define mmIH_VF_RB1_STATUS2_DEFAULT                     0x0000
#define mmIH_VF_RB1_STATUS_DEFAULT                      0x0000
#define mmIH_VF_RB2_STATUS2_DEFAULT                     0x0000
#define mmIH_VF_RB2_STATUS_DEFAULT                      0x0000
#define mmIH_VF_RB_STATUS2_DEFAULT                      0x0000
#define mmIH_VF_RB_STATUS_DEFAULT                       0x0000
#define mmIH_VIRT_RESET_REQ_DEFAULT                     0x0000
#define mmIH_VMID_0_LUT_DEFAULT                         0x0000
#define mmIH_VMID_0_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_10_LUT_DEFAULT                        0x0000
#define mmIH_VMID_10_LUT_MM_DEFAULT                     0x0000
#define mmIH_VMID_11_LUT_DEFAULT                        0x0000
#define mmIH_VMID_11_LUT_MM_DEFAULT                     0x0000
#define mmIH_VMID_12_LUT_DEFAULT                        0x0000
#define mmIH_VMID_12_LUT_MM_DEFAULT                     0x0000
#define mmIH_VMID_13_LUT_DEFAULT                        0x0000
#define mmIH_VMID_13_LUT_MM_DEFAULT                     0x0000
#define mmIH_VMID_14_LUT_DEFAULT                        0x0000
#define mmIH_VMID_14_LUT_MM_DEFAULT                     0x0000
#define mmIH_VMID_15_LUT_DEFAULT                        0x0000
#define mmIH_VMID_15_LUT_MM_DEFAULT                     0x0000
#define mmIH_VMID_1_LUT_DEFAULT                         0x0000
#define mmIH_VMID_1_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_2_LUT_DEFAULT                         0x0000
#define mmIH_VMID_2_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_3_LUT_DEFAULT                         0x0000
#define mmIH_VMID_3_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_4_LUT_DEFAULT                         0x0000
#define mmIH_VMID_4_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_5_LUT_DEFAULT                         0x0000
#define mmIH_VMID_5_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_6_LUT_DEFAULT                         0x0000
#define mmIH_VMID_6_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_7_LUT_DEFAULT                         0x0000
#define mmIH_VMID_7_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_8_LUT_DEFAULT                         0x0000
#define mmIH_VMID_8_LUT_MM_DEFAULT                      0x0000
#define mmIH_VMID_9_LUT_DEFAULT                         0x0000
#define mmIH_VMID_9_LUT_MM_DEFAULT                      0x0000
#define mmLDS_CONFIG_DEFAULT                            0x0000
#define mmMC_MEM_POWER_LS_DEFAULT__GFX09                0x0208
#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT__GFX09       0x0000
#define mmMC_VM_AGP_BASE_DEFAULT__GFX09                 0x0000
#define mmMC_VM_AGP_BOT_DEFAULT__GFX09                  0x0000
#define mmMC_VM_AGP_TOP_DEFAULT__GFX09                  0x0000
#define mmMC_VM_APT_CNTL_DEFAULT__GFX09                 0x0000
#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT__GFX09 0x0000
#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT__GFX09 0x0000
#define mmMC_VM_FB_LOCATION_BASE_DEFAULT__GFX09         0x0000
#define mmMC_VM_FB_LOCATION_TOP_DEFAULT__GFX09          0x0000
#define mmMC_VM_FB_OFFSET_DEFAULT__GFX09                0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT__GFX09      0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT__GFX09      0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT__GFX09      0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT__GFX09      0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT__GFX09      0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT__GFX09      0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT__GFX09       0x0000
#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT__GFX09       0x0000
#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT__GFX09      0x0000
#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT__GFX09        0x0000
#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT__GFX09        0x0000
#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT__GFX09 0x4000000
#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT__GFX09    0xFFFFF
#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT__GFX09 0x0000
#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT__GFX09  0x0000
#define mmMC_VM_MARC_BASE_HI_0_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_HI_1_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_HI_2_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_HI_3_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_LO_0_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_LO_1_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_LO_2_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_BASE_LO_3_DEFAULT__GFX09           0x0000
#define mmMC_VM_MARC_LEN_HI_0_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_HI_1_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_HI_2_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_HI_3_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_LO_0_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_LO_1_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_LO_2_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_LEN_LO_3_DEFAULT__GFX09            0x0000
#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT__GFX09          0x0000
#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT__GFX09          0x0000
#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT__GFX09           0x2501
#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT__GFX09    0x0000
#define mmMC_VM_NB_MMIOBASE_DEFAULT__GFX09              0x0000
#define mmMC_VM_NB_MMIOLIMIT_DEFAULT__GFX09             0x0000
#define mmMC_VM_NB_PCI_ARB_DEFAULT__GFX09               0x0008
#define mmMC_VM_NB_PCI_CTRL_DEFAULT__GFX09              0x0000
#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT__GFX09     0x0000
#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT__GFX09    0x0000
#define mmMC_VM_STEERING_DEFAULT__GFX09                 0x0001
#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT__GFX09 0x0000
#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT__GFX09 0x0000
#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT__GFX09 0x0000
#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT__GFX09 0x0000
#define mmMP0_SMN_ACTIVE_FCN_ID_DEFAULT__GFX09          0x0000
#define mmMP0_SMN_C2PMSG_100_DEFAULT__GFX09             0x0000
#define mmMP0_SMN_C2PMSG_101_DEFAULT__GFX09             0x0000
#define mmMP0_SMN_C2PMSG_102_DEFAULT__GFX09             0x0000
#define mmMP0_SMN_C2PMSG_103_DEFAULT__GFX09             0x0000
#define mmMP0_SMN_C2PMSG_32_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_33_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_34_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_35_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_36_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_37_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_38_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_39_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_40_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_41_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_42_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_43_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_44_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_45_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_46_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_47_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_48_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_49_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_50_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_51_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_52_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_53_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_54_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_55_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_56_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_57_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_58_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_59_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_60_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_61_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_62_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_63_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_64_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_65_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_66_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_67_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_68_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_69_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_70_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_71_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_72_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_73_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_74_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_75_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_76_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_77_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_78_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_79_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_80_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_81_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_82_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_83_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_84_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_85_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_86_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_87_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_88_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_89_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_90_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_91_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_92_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_93_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_94_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_95_DEFAULT                     0x0000
#define mmMP0_SMN_C2PMSG_96_DEFAULT__GFX09              0x0000
#define mmMP0_SMN_C2PMSG_97_DEFAULT__GFX09              0x0000
#define mmMP0_SMN_C2PMSG_98_DEFAULT__GFX09              0x0000
#define mmMP0_SMN_C2PMSG_99_DEFAULT__GFX09              0x0000
#define mmMP0_SMN_IH_CREDIT_DEFAULT__GFX09              0x0000
#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT__GFX09         0x0000
#define mmMP0_SMN_IH_SW_INT_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_ACP2MP_RESP_DEFAULT                   0x0000
#define mmMP1_SMN_ACTIVE_FCN_ID_DEFAULT__GFX09          0x0000
#define mmMP1_SMN_C2PMSG_100_DEFAULT__GFX09             0x0000
#define mmMP1_SMN_C2PMSG_101_DEFAULT__GFX09             0x0000
#define mmMP1_SMN_C2PMSG_102_DEFAULT__GFX09             0x0000
#define mmMP1_SMN_C2PMSG_103_DEFAULT__GFX09             0x0000
#define mmMP1_SMN_C2PMSG_32_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_33_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_34_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_35_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_36_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_37_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_38_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_39_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_40_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_41_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_42_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_43_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_44_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_45_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_46_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_47_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_48_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_49_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_50_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_51_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_52_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_53_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_54_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_55_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_56_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_57_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_58_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_59_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_60_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_61_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_62_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_63_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_64_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_65_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_66_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_67_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_68_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_69_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_70_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_71_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_72_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_73_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_74_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_75_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_76_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_77_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_78_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_79_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_80_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_81_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_82_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_83_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_84_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_85_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_86_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_87_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_88_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_89_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_90_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_91_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_92_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_93_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_94_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_95_DEFAULT                     0x0000
#define mmMP1_SMN_C2PMSG_96_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_C2PMSG_97_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_C2PMSG_98_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_C2PMSG_99_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_DC2MP_RESP_DEFAULT                    0x0000
#define mmMP1_SMN_EXT_SCRATCH0_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH1_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH2_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH3_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH4_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH5_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH6_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH7_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_EXT_SCRATCH8_DEFAULT__GFX09           0x0000
#define mmMP1_SMN_FPS_CNT_DEFAULT                       0x0000
#define mmMP1_SMN_IH_CREDIT_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_IH_SW_INT_DEFAULT__GFX09              0x0000
#define mmMP1_SMN_PUB_CTRL_DEFAULT__GFX09               0x0001
#define mmMP1_SMN_RLC2MP_RESP_DEFAULT                   0x0000
#define mmMP1_SMN_UVD2MP_RESP_DEFAULT                   0x0000
#define mmMP1_SMN_VCE2MP_RESP_DEFAULT                   0x0000
#define mmPA_CL_CLIP_CNTL_DEFAULT                       0xD4DC00D
#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT                0xCDCDCDCD
#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT                0xCDCDCDCD
#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT                0xCDCDCDCD
#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT                0xCDCDCDCD
#define mmPA_CL_NANINF_CNTL_DEFAULT                     0x4DCD
#define mmPA_CL_NGG_CNTL_DEFAULT                        0x0001
#define mmPA_CL_POINT_CULL_RAD_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_POINT_SIZE_DEFAULT                      0xCDCDCDCD
#define mmPA_CL_POINT_X_RAD_DEFAULT                     0xCDCDCDCD
#define mmPA_CL_POINT_Y_RAD_DEFAULT                     0xCDCDCDCD
#define mmPA_CL_RESET_DEBUG_DEFAULT                     0x0000
#define mmPA_CL_UCP_0_W_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_0_X_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_0_Y_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_0_Z_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_1_W_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_1_X_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_1_Y_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_1_Z_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_2_W_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_2_X_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_2_Y_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_2_Z_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_3_W_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_3_X_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_3_Y_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_3_Z_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_4_W_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_4_X_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_4_Y_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_4_Z_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_5_W_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_5_X_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_5_Y_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_UCP_5_Z_DEFAULT                         0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XOFFSET_DEFAULT                   0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_10_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_11_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_12_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_13_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_14_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_15_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_1_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_2_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_3_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_4_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_5_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_6_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_7_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_8_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_9_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_XSCALE_DEFAULT                    0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YOFFSET_DEFAULT                   0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_10_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_11_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_12_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_13_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_14_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_15_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_1_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_2_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_3_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_4_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_5_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_6_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_7_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_8_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_9_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_YSCALE_DEFAULT                    0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT                0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZOFFSET_DEFAULT                   0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT                 0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT                  0xCDCDCDCD
#define mmPA_CL_VPORT_ZSCALE_DEFAULT                    0xCDCDCDCD
#define mmPA_CL_VS_OUT_CNTL_DEFAULT                     0xDCDCDCD
#define mmPA_CL_VTE_CNTL_DEFAULT                        0x0D0D
#define mmPA_SC_AA_CONFIG_DEFAULT                       0xD41C005
#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT               0xCDCDCDCD
#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT               0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT     0xCDCDCDCD
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT     0xCDCDCDCD
#define mmPA_SC_BINNER_CNTL_1_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT             0x842A4402
#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT              0x0000
#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT              0x0000
#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT              0x0000
#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT              0x0000
#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT          0x0000
#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT             0xCDCDCDCD
#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT             0xCDCDCDCD
#define mmPA_SC_CLIPRECT_0_BR_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_0_TL_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_1_BR_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_1_TL_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_2_BR_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_2_TL_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_3_BR_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_3_TL_DEFAULT                   0x4DCD4DCD
#define mmPA_SC_CLIPRECT_RULE_DEFAULT                   0xCDCD
#define mmPA_SC_DSM_CNTL_DEFAULT                        0x0000
#define mmPA_SC_EDGERULE_DEFAULT                        0xCDCDCDCD
#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT                 0x0100
#define mmPA_SC_FIFO_SIZE_DEFAULT                       0x0000
#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT              0xFFFFFF
#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_HORIZ_GRID_DEFAULT                      0xCDCDCDCD
#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT          0xCDCD
#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT          0x0000
#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT        0x0000
#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT              0x0DCD
#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT     0xCDCD
#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT              0x0DCD
#define mmPA_SC_IF_FIFO_SIZE_DEFAULT                    0x0000
#define mmPA_SC_LEFT_VERT_GRID_DEFAULT                  0xCDCDCDCD
#define mmPA_SC_LINE_CNTL_DEFAULT                       0x0C00
#define mmPA_SC_LINE_STIPPLE_DEFAULT                    0x40CDCDCD
#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT              0x0000
#define mmPA_SC_MODE_CNTL_0_DEFAULT                     0x0045
#define mmPA_SC_MODE_CNTL_1_DEFAULT                     0x6000000
#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT           0xCDCD
#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT           0x0000
#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT         0x0000
#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT               0x0DCD
#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT      0xCDCD
#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT               0x0DCD
#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT             0x01CD
#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT             0x0000
#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT                 0xCDCDCDCD
#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT           0x0000
#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT             0x80008000
#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT             0x80008000
#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT             0x7FFF7FFF
#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT             0x7FFF7FFF
#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT               0xCDCDCDCD
#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT               0xCDCDCDCD
#define mmPA_SC_SHADER_CONTROL_DEFAULT                  0x0000
#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT    0x0000
#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT               0xCDCD
#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT               0x0000
#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT             0x0000
#define mmPA_SC_TRAP_SCREEN_H_DEFAULT                   0x0DCD
#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT          0xCDCD
#define mmPA_SC_TRAP_SCREEN_V_DEFAULT                   0x0DCD
#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT             0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT             0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT             0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT             0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT             0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT             0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT             0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT             0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT             0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT             0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT             0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT             0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT              0x4DCD4DCD
#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT              0xCDCD4DCD
#define mmPA_SC_VPORT_ZMAX_0_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_10_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_11_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_12_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_13_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_14_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_15_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_1_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_2_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_3_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_4_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_5_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_6_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_7_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_8_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMAX_9_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_0_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_10_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_11_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_12_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_13_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_14_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_15_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_1_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_2_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_3_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_4_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_5_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_6_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_7_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_8_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_VPORT_ZMIN_9_DEFAULT                    0xCDCDCDCD
#define mmPA_SC_WINDOW_OFFSET_DEFAULT                   0xCDCDCDCD
#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT               0x4DCD4DCD
#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT               0xCDCD4DCD
#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT            0x8000020
#define mmPA_SU_CNTL_STATUS_DEFAULT                     0x80000000
#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT          0x1CD01CD
#define mmPA_SU_LINE_CNTL_DEFAULT                       0xCDCD
#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT               0x000D
#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT              0xCDCDCDCD
#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT              0xCDCDCD
#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT         0x000D
#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT                 0xCDCD
#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT                 0xCDCD
#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT                 0xCDCD
#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT                 0xCDCD
#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT                 0xCDCDCDCD
#define mmPA_SU_POINT_MINMAX_DEFAULT                    0xCDCDCDCD
#define mmPA_SU_POINT_SIZE_DEFAULT                      0xCDCDCDCD
#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT         0xCDCDCDCD
#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT          0xCDCDCDCD
#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT               0xCDCDCDCD
#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT         0x01CD
#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT        0xCDCDCDCD
#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT         0xCDCDCDCD
#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT                0xC000CDCD
#define mmPA_SU_VTX_CNTL_DEFAULT                        0x000D
#define mmPA_UTCL1_CNTL1_DEFAULT__GFX09                 0x0600
#define mmPA_UTCL1_CNTL2_DEFAULT__GFX09                 0x0000
#define mmRAS_BCI_SIGNATURE0_DEFAULT                    0x0000
#define mmRAS_BCI_SIGNATURE1_DEFAULT                    0x0000
#define mmRAS_CB_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_DB_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_IA_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_IA_SIGNATURE1_DEFAULT                     0x0000
#define mmRAS_PA_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE1_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE2_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE3_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE4_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE5_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE6_DEFAULT                     0x0000
#define mmRAS_SC_SIGNATURE7_DEFAULT                     0x0000
#define mmRAS_SIGNATURE_CONTROL_DEFAULT                 0x0000
#define mmRAS_SIGNATURE_MASK_DEFAULT                    0x0000
#define mmRAS_SQ_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_SX_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_SX_SIGNATURE1_DEFAULT                     0x0000
#define mmRAS_SX_SIGNATURE2_DEFAULT                     0x0000
#define mmRAS_SX_SIGNATURE3_DEFAULT                     0x0000
#define mmRAS_TA_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_TA_SIGNATURE1_DEFAULT                     0x0000
#define mmRAS_TD_SIGNATURE0_DEFAULT                     0x0000
#define mmRAS_VGT_SIGNATURE0_DEFAULT                    0x0000
#define mmRLC_AUTO_PG_CTRL_DEFAULT                      0x0000
#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT           0x0000
#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT                 0x1003C
#define mmRLC_CGCG_CGLS_CTRL_DEFAULT                    0x1003C
#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT                 0x21711
#define mmRLC_CGCG_RAMP_CTRL_DEFAULT                    0x21711
#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT                0xFFFFFFFF
#define mmRLC_CNTL_DEFAULT                              0x0001
#define mmRLC_CP_EOF_INT_CNT_DEFAULT                    0x0000
#define mmRLC_CP_EOF_INT_DEFAULT                        0x0000
#define mmRLC_CP_SCHEDULERS_DEFAULT                     0x58504840
#define mmRLC_CSIB_ADDR_HI_DEFAULT                      0x0000
#define mmRLC_CSIB_ADDR_LO_DEFAULT                      0x0000
#define mmRLC_CSIB_LENGTH_DEFAULT                       0x0000
#define mmRLC_CU_STATUS_DEFAULT__GFX09                  0x0000
#define mmRLC_DSM_TRIG_DEFAULT__GFX09                   0x0000
#define mmRLC_DS_CNTL_DEFAULT__GFX09                    0x30003
#define mmRLC_DYN_PG_REQUEST_DEFAULT                    0xFFFFFFFF
#define mmRLC_DYN_PG_STATUS_DEFAULT                     0xFFFFFFFF
#define mmRLC_FIREWALL_VIOLATION_DEFAULT                0x0000
#define mmRLC_GFX_RM_CNTL_DEFAULT                       0x0000
#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT            0x0000
#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT            0x0000
#define mmRLC_GPM_GENERAL_0_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_10_DEFAULT                    0x0000
#define mmRLC_GPM_GENERAL_11_DEFAULT                    0x0000
#define mmRLC_GPM_GENERAL_12_DEFAULT                    0x0000
#define mmRLC_GPM_GENERAL_1_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_2_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_3_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_4_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_5_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_6_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_7_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_8_DEFAULT                     0x0000
#define mmRLC_GPM_GENERAL_9_DEFAULT                     0x0000
#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT__GFX09        0x0000
#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT                 0x0000
#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT__GFX09          0x0000
#define mmRLC_GPM_LOG_CONT_DEFAULT                      0x0000
#define mmRLC_GPM_LOG_SIZE_DEFAULT                      0x0000
#define mmRLC_GPM_PERF_COUNT_0_DEFAULT                  0x0000
#define mmRLC_GPM_PERF_COUNT_1_DEFAULT                  0x0000
#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT                  0x0000
#define mmRLC_GPM_SCRATCH_DATA_DEFAULT                  0x0000
#define mmRLC_GPM_THREAD_ENABLE_DEFAULT                 0x0001
#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT               0x8080808
#define mmRLC_GPM_TIMER_CTRL_DEFAULT                    0x0000
#define mmRLC_GPM_TIMER_STAT_DEFAULT                    0x0000
#define mmRLC_GPM_UCODE_ADDR_DEFAULT                    0x0000
#define mmRLC_GPM_UCODE_DATA_DEFAULT                    0x0000
#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT                  0x0080
#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT                  0x0080
#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT                  0x0080
#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT             0x0000
#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT             0x0000
#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT             0x0000
#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT             0x0000
#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT             0x0000
#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT             0x0000
#define mmRLC_GPR_REG1_DEFAULT                          0x0000
#define mmRLC_GPR_REG2_DEFAULT                          0x0000
#define mmRLC_GPU_CLOCK_32_DEFAULT                      0x0000
#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT              0x0000
#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT               0x0000
#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT               0x0000
#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT             0x0000
#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT                  0x0000
#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT                  0x0000
#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT                  0x0000
#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT                  0x0000
#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT                  0x0000
#define mmRLC_GPU_IOV_F32_RESET_DEFAULT                 0x0000
#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT                 0x0000
#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT             0x0000
#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT          0x0000
#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT          0x0000
#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT          0x0000
#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT          0x0000
#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT              0x0000
#define mmRLC_GPU_IOV_SCH_0_DEFAULT                     0x0000
#define mmRLC_GPU_IOV_SCH_1_DEFAULT                     0x0000
#define mmRLC_GPU_IOV_SCH_2_DEFAULT                     0x0000
#define mmRLC_GPU_IOV_SCH_3_DEFAULT                     0x0000
#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT                 0x0000
#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT              0x0000
#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT              0x0000
#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT         0x0000
#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT              0x0000
#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT         0x0000
#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT              0x0000
#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT              0x0000
#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT                0x0000
#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT                0x0000
#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT    0x0000
#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT    0x0000
#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT                 0x0000
#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT            0x0000
#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT            0x0000
#define mmRLC_HYP_SEMAPHORE_2_DEFAULT                   0x0000
#define mmRLC_HYP_SEMAPHORE_3_DEFAULT                   0x0000
#define mmRLC_INT_STAT_DEFAULT                          0x0000
#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT                0x0000
#define mmRLC_LBPW_CU_STAT_DEFAULT__GFX09               0x0000
#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT__GFX09   0x0001
#define mmRLC_LB_CNTR_INIT_DEFAULT__GFX09               0x0000
#define mmRLC_LB_CNTR_MAX_DEFAULT__GFX09                0xFFFFFFFF
#define mmRLC_LB_INIT_CU_MASK_DEFAULT__GFX09            0xFFFFFFFF
#define mmRLC_LB_PARAMS_DEFAULT                         0x601008
#define mmRLC_LB_THR_CONFIG_1_DEFAULT__GFX09            0x0000
#define mmRLC_LB_THR_CONFIG_2_DEFAULT__GFX09            0x0000
#define mmRLC_LB_THR_CONFIG_3_DEFAULT__GFX09            0x0000
#define mmRLC_LB_THR_CONFIG_4_DEFAULT__GFX09            0x0000
#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT__GFX09          0x0000
#define mmRLC_MAX_PG_CU_DEFAULT__GFX09                  0x0000
#define mmRLC_MEM_SLP_CNTL_DEFAULT                      0x20200
#define mmRLC_MGCG_CTRL_DEFAULT                         0x18800
#define mmRLC_PERFCOUNTER0_HI_DEFAULT                   0xCDCDCDCD
#define mmRLC_PERFCOUNTER0_LO_DEFAULT                   0xCDCDCDCD
#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT               0x0000
#define mmRLC_PERFCOUNTER1_HI_DEFAULT                   0xCDCDCDCD
#define mmRLC_PERFCOUNTER1_LO_DEFAULT                   0xCDCDCDCD
#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT               0x0000
#define mmRLC_PERFMON_CLK_CNTL_DEFAULT                  0x0001
#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT__GFX09       0x0003
#define mmRLC_PG_CNTL_DEFAULT                           0x0000
#define mmRLC_PG_DELAY_2_DEFAULT                        0x0004
#define mmRLC_PG_DELAY_3_DEFAULT                        0x0000
#define mmRLC_PG_DELAY_DEFAULT                          0x101010
#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT          0x0000
#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT          0x0000
#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT              0x0080
#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT          0x0000
#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT          0x0000
#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT              0x0000
#define mmRLC_R2I_CNTL_0_DEFAULT                        0x0000
#define mmRLC_R2I_CNTL_1_DEFAULT                        0x0000
#define mmRLC_R2I_CNTL_2_DEFAULT                        0x0000
#define mmRLC_R2I_CNTL_3_DEFAULT                        0x0000
#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT            0x0000
#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT            0x0000
#define mmRLC_RLCV_COMMAND_DEFAULT                      0x0000
#define mmRLC_RLCV_SAFE_MODE_DEFAULT                    0x0000
#define mmRLC_RLCV_SPARE_INT_DEFAULT                    0x0000
#define mmRLC_RLCV_TIMER_CTRL_DEFAULT                   0x0000
#define mmRLC_RLCV_TIMER_INT_0_DEFAULT                  0x0000
#define mmRLC_RLCV_TIMER_STAT_DEFAULT                   0x0000
#define mmRLC_SAFE_MODE_DEFAULT                         0x0000
#define mmRLC_SEMAPHORE_0_DEFAULT                       0x0000
#define mmRLC_SEMAPHORE_1_DEFAULT                       0x0000
#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT__GFX09      0x0000
#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT__GFX09 0x0000
#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT__GFX09   0x0000
#define mmRLC_SERDES_RD_DATA_0_DEFAULT                  0x0000
#define mmRLC_SERDES_RD_DATA_1_DEFAULT                  0x0000
#define mmRLC_SERDES_RD_DATA_2_DEFAULT                  0x0000
#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT__GFX09     0x0000
#define mmRLC_SERDES_WR_CTRL_DEFAULT__GFX09             0x0000
#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT__GFX09   0x0000
#define mmRLC_SERDES_WR_DATA_DEFAULT__GFX09             0x0000
#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT__GFX09 0x0000
#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT__GFX09 0x0000
#define mmRLC_SMU_ARGUMENT_1_DEFAULT                    0x0000
#define mmRLC_SMU_ARGUMENT_2_DEFAULT                    0x0000
#define mmRLC_SMU_COMMAND_DEFAULT                       0x0000
#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT            0x0000
#define mmRLC_SMU_MESSAGE_DEFAULT                       0x0000
#define mmRLC_SMU_SAFE_MODE_DEFAULT                     0x0000
#define mmRLC_SPARE_INT_DEFAULT                         0x0000
#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT            0x0000
#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT            0x0000
#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_INT_CNTL_DEFAULT                      0x0000
#define mmRLC_SPM_INT_STATUS_DEFAULT                    0x0000
#define mmRLC_SPM_MC_CNTL_DEFAULT                       0x0000
#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_PERFMON_CNTL_DEFAULT                  0x0000
#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT          0x0000
#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT          0x0000
#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT             0x0000
#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT          0x0000
#define mmRLC_SPM_RING_RDPTR_DEFAULT                    0x0000
#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT             0x0000
#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT                0x0000
#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT                0x0000
#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SPM_UTCL1_CNTL_DEFAULT                    0x0080
#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT                 0x0000
#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT                 0x0000
#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT__GFX09 0x0000
#define mmRLC_SRM_ARAM_ADDR_DEFAULT                     0x0000
#define mmRLC_SRM_ARAM_DATA_DEFAULT                     0x0000
#define mmRLC_SRM_CNTL_DEFAULT                          0x0002
#define mmRLC_SRM_DRAM_ADDR_DEFAULT                     0x0000
#define mmRLC_SRM_DRAM_DATA_DEFAULT                     0x0000
#define mmRLC_SRM_GPM_ABORT_DEFAULT                     0x0000
#define mmRLC_SRM_GPM_COMMAND_DEFAULT                   0x0000
#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT            0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT             0x0000
#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT             0x0000
#define mmRLC_SRM_RLCV_COMMAND_DEFAULT                  0x0000
#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT           0x0000
#define mmRLC_SRM_STAT_DEFAULT                          0x0000
#define mmRLC_STATIC_PG_STATUS_DEFAULT                  0xFFFFFFFF
#define mmRLC_STAT_DEFAULT                              0x0000
#define mmRLC_THREAD1_DELAY_DEFAULT__GFX09              0x400401
#define mmRLC_UCODE_CNTL_DEFAULT                        0x0000
#define mmRLC_UTCL1_STATUS_2_DEFAULT                    0x0000
#define mmRLC_UTCL1_STATUS_DEFAULT                      0x0000
#define mmRLC_UTCL2_CNTL_DEFAULT__GFX09                 0x0000
#define mmRMI_CGTT_SCLK_CTRL_DEFAULT                    0x0100
#define mmRMI_CLOCK_CNTRL_DEFAULT                       0x4208822
#define mmRMI_DEMUX_CNTL_DEFAULT                        0x2000200
#define mmRMI_GENERAL_CNTL_DEFAULT                      0x0000
#define mmRMI_GENERAL_STATUS_DEFAULT                    0x0000
#define mmRMI_PERFCOUNTER0_HI_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER0_LO_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT              0x0000
#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT               0x0000
#define mmRMI_PERFCOUNTER1_HI_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER1_LO_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT               0x0000
#define mmRMI_PERFCOUNTER2_HI_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER2_LO_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT              0x0000
#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT               0x0000
#define mmRMI_PERFCOUNTER3_HI_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER3_LO_DEFAULT                   0x0000
#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT               0x0000
#define mmRMI_PERF_COUNTER_CNTL_DEFAULT                 0x80240
#define mmRMI_SCOREBOARD_CNTL_DEFAULT                   0x1FFE00
#define mmRMI_SCOREBOARD_STATUS0_DEFAULT                0x0000
#define mmRMI_SCOREBOARD_STATUS1_DEFAULT                0x0000
#define mmRMI_SCOREBOARD_STATUS2_DEFAULT                0x0000
#define mmRMI_SPARE_1_DEFAULT                           0x0000
#define mmRMI_SPARE_2_DEFAULT                           0x0000
#define mmRMI_SUBBLOCK_STATUS0_DEFAULT                  0x0000
#define mmRMI_SUBBLOCK_STATUS1_DEFAULT                  0x0000
#define mmRMI_SUBBLOCK_STATUS2_DEFAULT                  0x0000
#define mmRMI_SUBBLOCK_STATUS3_DEFAULT                  0x0000
#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT              0x4404001E
#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT              0x4404001E
#define mmRMI_UTCL1_CNTL1_DEFAULT                       0x20000
#define mmRMI_UTCL1_CNTL2_DEFAULT                       0x10000
#define mmRMI_UTCL1_STATUS_DEFAULT                      0x0000
#define mmRMI_UTC_UNIT_CONFIG_DEFAULT                   0x0000
#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT             0x0564
#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT             0xFFFFFFFF
#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT               0x8000800
#define mmRMI_XBAR_CONFIG_DEFAULT                       0x0F00
#define mmRMI_XNACK_DEBUG_DEFAULT                       0x0000
#define mmROM_CNTL_DEFAULT                              0x0000
#define mmROM_DATA_DEFAULT                              0x0000
#define mmROM_INDEX_DEFAULT                             0x0000
#define mmROM_START_DEFAULT                             0x0000
#define mmROM_STATUS_DEFAULT                            0x0000
#define mmROM_SW_CNTL_DEFAULT                           0x0000
#define mmROM_SW_COMMAND_DEFAULT                        0x0000
#define mmROM_SW_DATA_10_DEFAULT                        0x0000
#define mmROM_SW_DATA_11_DEFAULT                        0x0000
#define mmROM_SW_DATA_12_DEFAULT                        0x0000
#define mmROM_SW_DATA_13_DEFAULT                        0x0000
#define mmROM_SW_DATA_14_DEFAULT                        0x0000
#define mmROM_SW_DATA_15_DEFAULT                        0x0000
#define mmROM_SW_DATA_16_DEFAULT                        0x0000
#define mmROM_SW_DATA_17_DEFAULT                        0x0000
#define mmROM_SW_DATA_18_DEFAULT                        0x0000
#define mmROM_SW_DATA_19_DEFAULT                        0x0000
#define mmROM_SW_DATA_1_DEFAULT                         0x0000
#define mmROM_SW_DATA_20_DEFAULT                        0x0000
#define mmROM_SW_DATA_21_DEFAULT                        0x0000
#define mmROM_SW_DATA_22_DEFAULT                        0x0000
#define mmROM_SW_DATA_23_DEFAULT                        0x0000
#define mmROM_SW_DATA_24_DEFAULT                        0x0000
#define mmROM_SW_DATA_25_DEFAULT                        0x0000
#define mmROM_SW_DATA_26_DEFAULT                        0x0000
#define mmROM_SW_DATA_27_DEFAULT                        0x0000
#define mmROM_SW_DATA_28_DEFAULT                        0x0000
#define mmROM_SW_DATA_29_DEFAULT                        0x0000
#define mmROM_SW_DATA_2_DEFAULT                         0x0000
#define mmROM_SW_DATA_30_DEFAULT                        0x0000
#define mmROM_SW_DATA_31_DEFAULT                        0x0000
#define mmROM_SW_DATA_32_DEFAULT                        0x0000
#define mmROM_SW_DATA_33_DEFAULT                        0x0000
#define mmROM_SW_DATA_34_DEFAULT                        0x0000
#define mmROM_SW_DATA_35_DEFAULT                        0x0000
#define mmROM_SW_DATA_36_DEFAULT                        0x0000
#define mmROM_SW_DATA_37_DEFAULT                        0x0000
#define mmROM_SW_DATA_38_DEFAULT                        0x0000
#define mmROM_SW_DATA_39_DEFAULT                        0x0000
#define mmROM_SW_DATA_3_DEFAULT                         0x0000
#define mmROM_SW_DATA_40_DEFAULT                        0x0000
#define mmROM_SW_DATA_41_DEFAULT                        0x0000
#define mmROM_SW_DATA_42_DEFAULT                        0x0000
#define mmROM_SW_DATA_43_DEFAULT                        0x0000
#define mmROM_SW_DATA_44_DEFAULT                        0x0000
#define mmROM_SW_DATA_45_DEFAULT                        0x0000
#define mmROM_SW_DATA_46_DEFAULT                        0x0000
#define mmROM_SW_DATA_47_DEFAULT                        0x0000
#define mmROM_SW_DATA_48_DEFAULT                        0x0000
#define mmROM_SW_DATA_49_DEFAULT                        0x0000
#define mmROM_SW_DATA_4_DEFAULT                         0x0000
#define mmROM_SW_DATA_50_DEFAULT                        0x0000
#define mmROM_SW_DATA_51_DEFAULT                        0x0000
#define mmROM_SW_DATA_52_DEFAULT                        0x0000
#define mmROM_SW_DATA_53_DEFAULT                        0x0000
#define mmROM_SW_DATA_54_DEFAULT                        0x0000
#define mmROM_SW_DATA_55_DEFAULT                        0x0000
#define mmROM_SW_DATA_56_DEFAULT                        0x0000
#define mmROM_SW_DATA_57_DEFAULT                        0x0000
#define mmROM_SW_DATA_58_DEFAULT                        0x0000
#define mmROM_SW_DATA_59_DEFAULT                        0x0000
#define mmROM_SW_DATA_5_DEFAULT                         0x0000
#define mmROM_SW_DATA_60_DEFAULT                        0x0000
#define mmROM_SW_DATA_61_DEFAULT                        0x0000
#define mmROM_SW_DATA_62_DEFAULT                        0x0000
#define mmROM_SW_DATA_63_DEFAULT                        0x0000
#define mmROM_SW_DATA_64_DEFAULT                        0x0000
#define mmROM_SW_DATA_6_DEFAULT                         0x0000
#define mmROM_SW_DATA_7_DEFAULT                         0x0000
#define mmROM_SW_DATA_8_DEFAULT                         0x0000
#define mmROM_SW_DATA_9_DEFAULT                         0x0000
#define mmROM_SW_STATUS_DEFAULT                         0x0000
#define mmRPB_ARB_CNTL2_DEFAULT                         0x40104
#define mmRPB_ARB_CNTL_DEFAULT                          0x40404
#define mmRPB_ATS_CNTL2_DEFAULT                         0x50B13
#define mmRPB_ATS_CNTL_DEFAULT                          0x58088422
#define mmRPB_BIF_CNTL_DEFAULT                          0x1000404
#define mmRPB_BLOCKLEVEL_CONF_DEFAULT                   0x00F0
#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT                 0x0000
#define mmRPB_CID_QUEUE_EX_DEFAULT                      0x0000
#define mmRPB_CID_QUEUE_RD_DEFAULT                      0x0000
#define mmRPB_CID_QUEUE_WR_DEFAULT                      0x0000
#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT             0x0004
#define mmRPB_EA_QUEUE_WR_DEFAULT                       0x0000
#define mmRPB_EFF_CNTL_DEFAULT                          0x1010
#define mmRPB_PASSPW_CONF_DEFAULT                       0x0230
#define mmRPB_PERFCOUNTER0_CFG_DEFAULT                  0x0000
#define mmRPB_PERFCOUNTER1_CFG_DEFAULT                  0x0000
#define mmRPB_PERFCOUNTER2_CFG_DEFAULT                  0x0000
#define mmRPB_PERFCOUNTER3_CFG_DEFAULT                  0x0000
#define mmRPB_PERFCOUNTER_HI_DEFAULT                    0x0000
#define mmRPB_PERFCOUNTER_LO_DEFAULT                    0x0000
#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT             0x4000000
#define mmRPB_RD_QUEUE_CNTL2_DEFAULT                    0x0000
#define mmRPB_RD_QUEUE_CNTL_DEFAULT                     0x0000
#define mmRPB_RD_SWITCH_CNTL_DEFAULT                    0x2040810
#define mmRPB_SWITCH_CNTL2_DEFAULT                      0x2040810
#define mmRPB_VC_SWITCH_RDWR_DEFAULT                    0x4040
#define mmRPB_WR_QUEUE_CNTL2_DEFAULT                    0x0000
#define mmRPB_WR_QUEUE_CNTL_DEFAULT                     0x0000
#define mmRPB_WR_SWITCH_CNTL_DEFAULT                    0x2040810
#define mmSCRATCH_ADDR_DEFAULT                          0x0000
#define mmSCRATCH_REG0_DEFAULT                          0x0000
#define mmSCRATCH_REG1_DEFAULT                          0x0000
#define mmSCRATCH_REG2_DEFAULT                          0x0000
#define mmSCRATCH_REG3_DEFAULT                          0x0000
#define mmSCRATCH_REG4_DEFAULT                          0x0000
#define mmSCRATCH_REG5_DEFAULT                          0x0000
#define mmSCRATCH_REG6_DEFAULT                          0x0000
#define mmSCRATCH_REG7_DEFAULT                          0x0000
#define mmSCRATCH_UMSK_DEFAULT                          0x0000
#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT                   0x0000
#define mmSDMA0_ATOMIC_CNTL_DEFAULT                     0x0200
#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT                 0x0000
#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT                 0x0000
#define mmSDMA0_BA_THRESHOLD_DEFAULT                    0x3FF03FF
#define mmSDMA0_CHICKEN_BITS_2_DEFAULT                  0x0005
#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT__GFX09   0x0000
#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT               0xFFFDF79F
#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT               0x3FBCFF
#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT               0x03FF
#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT               0x0000
#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT               0x0000
#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT              0x0000
#define mmSDMA0_EDC_CONFIG_DEFAULT                      0x0002
#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT               0x0000
#define mmSDMA0_EDC_COUNTER_DEFAULT                     0x0000
#define mmSDMA0_ERROR_LOG_DEFAULT                       0x000F
#define mmSDMA0_F32_CNTL_DEFAULT                        0x0001
#define mmSDMA0_F32_COUNTER_DEFAULT                     0x0000
#define mmSDMA0_FREEZE_DEFAULT                          0x0000
#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT                0x0000
#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT              0x0005
#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT                 0x0000
#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT                 0x0000
#define mmSDMA0_GFX_DOORBELL_DEFAULT                    0x0000
#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT                0x0000
#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT             0x0000
#define mmSDMA0_GFX_DUMMY_REG_DEFAULT                   0x000F
#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT                  0x0000
#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT                  0x0000
#define mmSDMA0_GFX_IB_CNTL_DEFAULT                     0x0100
#define mmSDMA0_GFX_IB_OFFSET_DEFAULT                   0x0000
#define mmSDMA0_GFX_IB_RPTR_DEFAULT                     0x0000
#define mmSDMA0_GFX_IB_SIZE_DEFAULT                     0x0000
#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT               0x0000
#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT                 0x0000
#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT                0x0000
#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT                0x0000
#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT            0x0000
#define mmSDMA0_GFX_PREEMPT_DEFAULT                     0x0000
#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT                 0x4000
#define mmSDMA0_GFX_RB_BASE_DEFAULT                     0x0000
#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT                  0x0000
#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT             0x0000
#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT             0x0000
#define mmSDMA0_GFX_RB_RPTR_DEFAULT                     0x0000
#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT                  0x0000
#define mmSDMA0_GFX_RB_WPTR_DEFAULT                     0x0000
#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT                  0x0000
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT        0x0000
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT        0x0000
#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT           0x401000
#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT                   0x0000
#define mmSDMA0_GFX_STATUS_DEFAULT                      0x0000
#define mmSDMA0_GFX_WATERMARK_DEFAULT                   0x0000
#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT           0x0000
#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT                 0x0000
#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT                 0x0000
#define mmSDMA0_ID_DEFAULT                              0x0001
#define mmSDMA0_MMHUB_CNTL_DEFAULT__GFX09               0x0000
#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT__GFX09           0x0000
#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT             0x0004
#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT                0x0000
#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT                0x0000
#define mmSDMA0_PAGE_DOORBELL_DEFAULT                   0x0000
#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT               0x0000
#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT            0x0000
#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT                  0x000F
#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT                 0x0000
#define mmSDMA0_PAGE_IB_CNTL_DEFAULT                    0x0100
#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT                  0x0000
#define mmSDMA0_PAGE_IB_RPTR_DEFAULT                    0x0000
#define mmSDMA0_PAGE_IB_SIZE_DEFAULT                    0x0000
#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT              0x0000
#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT                0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT               0x0000
#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT               0x0000
#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT           0x0000
#define mmSDMA0_PAGE_PREEMPT_DEFAULT                    0x0000
#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT                0x4000
#define mmSDMA0_PAGE_RB_BASE_DEFAULT                    0x0000
#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT            0x0000
#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT            0x0000
#define mmSDMA0_PAGE_RB_RPTR_DEFAULT                    0x0000
#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT                 0x0000
#define mmSDMA0_PAGE_RB_WPTR_DEFAULT                    0x0000
#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT                 0x0000
#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT       0x0000
#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT       0x0000
#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT          0x401000
#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT                  0x0000
#define mmSDMA0_PAGE_STATUS_DEFAULT                     0x0000
#define mmSDMA0_PAGE_WATERMARK_DEFAULT                  0x0000
#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT             0x0000
#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT             0x0000
#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT     0x640000
#define mmSDMA0_PERFMON_CNTL_DEFAULT                    0xFF7FD
#define mmSDMA0_PHASE0_QUANTUM_DEFAULT                  0x10002
#define mmSDMA0_PHASE1_QUANTUM_DEFAULT                  0x10002
#define mmSDMA0_PHASE2_QUANTUM_DEFAULT                  0x10002
#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT                0x0000
#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT                0x0000
#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT                 0x6060200
#define mmSDMA0_PROGRAM_DEFAULT                         0x0000
#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT                  0x0000
#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT                  0x0000
#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT                  0x0000
#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT                  0x0000
#define mmSDMA0_PUB_REG_TYPE1_DEFAULT                   0x30003882
#define mmSDMA0_RB_RPTR_FETCH_DEFAULT                   0x0000
#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT                0x0000
#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT              0xC0000006
#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT             0x0004
#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT                0x0000
#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT                0x0000
#define mmSDMA0_RLC0_DOORBELL_DEFAULT                   0x0000
#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT               0x0000
#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT            0x0000
#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT                  0x000F
#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT                 0x0000
#define mmSDMA0_RLC0_IB_CNTL_DEFAULT                    0x0100
#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT                  0x0000
#define mmSDMA0_RLC0_IB_RPTR_DEFAULT                    0x0000
#define mmSDMA0_RLC0_IB_SIZE_DEFAULT                    0x0000
#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT              0x0000
#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT                0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT               0x0000
#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT               0x0000
#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT           0x0000
#define mmSDMA0_RLC0_PREEMPT_DEFAULT                    0x0000
#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT                0x4000
#define mmSDMA0_RLC0_RB_BASE_DEFAULT                    0x0000
#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT            0x0000
#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT            0x0000
#define mmSDMA0_RLC0_RB_RPTR_DEFAULT                    0x0000
#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC0_RB_WPTR_DEFAULT                    0x0000
#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT       0x0000
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT       0x0000
#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT          0x401000
#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT                  0x0000
#define mmSDMA0_RLC0_STATUS_DEFAULT                     0x0000
#define mmSDMA0_RLC0_WATERMARK_DEFAULT                  0x0000
#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT             0x0004
#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT                0x0000
#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT                0x0000
#define mmSDMA0_RLC1_DOORBELL_DEFAULT                   0x0000
#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT               0x0000
#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT            0x0000
#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT                  0x000F
#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT                 0x0000
#define mmSDMA0_RLC1_IB_CNTL_DEFAULT                    0x0100
#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT                  0x0000
#define mmSDMA0_RLC1_IB_RPTR_DEFAULT                    0x0000
#define mmSDMA0_RLC1_IB_SIZE_DEFAULT                    0x0000
#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT              0x0000
#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT                0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT               0x0000
#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT               0x0000
#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT           0x0000
#define mmSDMA0_RLC1_PREEMPT_DEFAULT                    0x0000
#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT                0x4000
#define mmSDMA0_RLC1_RB_BASE_DEFAULT                    0x0000
#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT            0x0000
#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT            0x0000
#define mmSDMA0_RLC1_RB_RPTR_DEFAULT                    0x0000
#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC1_RB_WPTR_DEFAULT                    0x0000
#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT                 0x0000
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT       0x0000
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT       0x0000
#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT          0x401000
#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT                  0x0000
#define mmSDMA0_RLC1_STATUS_DEFAULT                     0x0000
#define mmSDMA0_RLC1_WATERMARK_DEFAULT                  0x0000
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT        0x0000
#define mmSDMA0_STATUS1_REG_DEFAULT                     0x03FF
#define mmSDMA0_STATUS2_REG_DEFAULT                     0x0000
#define mmSDMA0_STATUS_REG_DEFAULT                      0x46DEE557
#define mmSDMA0_UCODE_ADDR_DEFAULT                      0x0000
#define mmSDMA0_UCODE_CHECKSUM_DEFAULT                  0x0000
#define mmSDMA0_UCODE_DATA_DEFAULT                      0x0000
#define mmSDMA0_ULV_CNTL_DEFAULT__GFX09                 0x0000
#define mmSDMA0_UNBREAKABLE_DEFAULT                     0x0000
#define mmSDMA0_UTCL1_INV1_DEFAULT                      0x0000
#define mmSDMA0_UTCL1_INV2_DEFAULT                      0x0000
#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT                 0x0000
#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT                 0x0000
#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT                 0x0000
#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT                 0x0000
#define mmSDMA0_VF_ENABLE_DEFAULT                       0x0000
#define mmSDMA0_VIRT_RESET_REQ_DEFAULT                  0x0000
#define mmSDMA0_VM_CNTL_DEFAULT                         0x0000
#define mmSDMA0_VM_CTX_HI_DEFAULT                       0x0000
#define mmSDMA0_VM_CTX_LO_DEFAULT                       0x0000
#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT                   0x0000
#define mmSDMA1_ATOMIC_CNTL_DEFAULT                     0x0200
#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT                 0x0000
#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT                 0x0000
#define mmSDMA1_BA_THRESHOLD_DEFAULT                    0x3FF03FF
#define mmSDMA1_CHICKEN_BITS_2_DEFAULT                  0x0005
#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT__GFX09   0x0000
#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT               0xFFFDF79F
#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT               0x3FBCFF
#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT               0x03FF
#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT               0x0000
#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT               0x0000
#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT              0x0000
#define mmSDMA1_EDC_CONFIG_DEFAULT                      0x0002
#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT               0x0000
#define mmSDMA1_EDC_COUNTER_DEFAULT                     0x0000
#define mmSDMA1_ERROR_LOG_DEFAULT                       0x000F
#define mmSDMA1_F32_CNTL_DEFAULT                        0x0001
#define mmSDMA1_F32_COUNTER_DEFAULT                     0x0000
#define mmSDMA1_FREEZE_DEFAULT                          0x0000
#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT                0x0000
#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT              0x0005
#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT                 0x0000
#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT                 0x0000
#define mmSDMA1_GFX_DOORBELL_DEFAULT                    0x0000
#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT                0x0000
#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT             0x0000
#define mmSDMA1_GFX_DUMMY_REG_DEFAULT                   0x000F
#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT                  0x0000
#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT                  0x0000
#define mmSDMA1_GFX_IB_CNTL_DEFAULT                     0x0100
#define mmSDMA1_GFX_IB_OFFSET_DEFAULT                   0x0000
#define mmSDMA1_GFX_IB_RPTR_DEFAULT                     0x0000
#define mmSDMA1_GFX_IB_SIZE_DEFAULT                     0x0000
#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT               0x0000
#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT                 0x0000
#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT                0x0000
#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT                0x0000
#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT            0x0000
#define mmSDMA1_GFX_PREEMPT_DEFAULT                     0x0000
#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT                 0x4000
#define mmSDMA1_GFX_RB_BASE_DEFAULT                     0x0000
#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT                  0x0000
#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT             0x0000
#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT             0x0000
#define mmSDMA1_GFX_RB_RPTR_DEFAULT                     0x0000
#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT                  0x0000
#define mmSDMA1_GFX_RB_WPTR_DEFAULT                     0x0000
#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT                  0x0000
#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT        0x0000
#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT        0x0000
#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT           0x401000
#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT                   0x0000
#define mmSDMA1_GFX_STATUS_DEFAULT                      0x0000
#define mmSDMA1_GFX_WATERMARK_DEFAULT                   0x0000
#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT           0x0000
#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT                 0x0000
#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT                 0x0000
#define mmSDMA1_ID_DEFAULT                              0x0001
#define mmSDMA1_MMHUB_CNTL_DEFAULT__GFX09               0x0000
#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT__GFX09           0x0000
#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT             0x0004
#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT                0x0000
#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT                0x0000
#define mmSDMA1_PAGE_DOORBELL_DEFAULT                   0x0000
#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT               0x0000
#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT            0x0000
#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT                  0x000F
#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT                 0x0000
#define mmSDMA1_PAGE_IB_CNTL_DEFAULT                    0x0100
#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT                  0x0000
#define mmSDMA1_PAGE_IB_RPTR_DEFAULT                    0x0000
#define mmSDMA1_PAGE_IB_SIZE_DEFAULT                    0x0000
#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT              0x0000
#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT                0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT               0x0000
#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT               0x0000
#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT           0x0000
#define mmSDMA1_PAGE_PREEMPT_DEFAULT                    0x0000
#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT                0x4000
#define mmSDMA1_PAGE_RB_BASE_DEFAULT                    0x0000
#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT            0x0000
#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT            0x0000
#define mmSDMA1_PAGE_RB_RPTR_DEFAULT                    0x0000
#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT                 0x0000
#define mmSDMA1_PAGE_RB_WPTR_DEFAULT                    0x0000
#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT                 0x0000
#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT       0x0000
#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT       0x0000
#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT          0x401000
#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT                  0x0000
#define mmSDMA1_PAGE_STATUS_DEFAULT                     0x0000
#define mmSDMA1_PAGE_WATERMARK_DEFAULT                  0x0000
#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT             0x0000
#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT             0x0000
#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT     0x640000
#define mmSDMA1_PERFMON_CNTL_DEFAULT                    0xFF7FD
#define mmSDMA1_PHASE0_QUANTUM_DEFAULT                  0x10002
#define mmSDMA1_PHASE1_QUANTUM_DEFAULT                  0x10002
#define mmSDMA1_PHASE2_QUANTUM_DEFAULT                  0x10002
#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT                0x0000
#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT                0x0000
#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT                 0x6060200
#define mmSDMA1_PROGRAM_DEFAULT                         0x0000
#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT                  0x0000
#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT                  0x0000
#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT                  0x0000
#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT                  0x0000
#define mmSDMA1_PUB_REG_TYPE1_DEFAULT                   0x30003882
#define mmSDMA1_RB_RPTR_FETCH_DEFAULT                   0x0000
#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT                0x0000
#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT              0xC0000006
#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT             0x0004
#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT                0x0000
#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT                0x0000
#define mmSDMA1_RLC0_DOORBELL_DEFAULT                   0x0000
#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT               0x0000
#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT            0x0000
#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT                  0x000F
#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT                 0x0000
#define mmSDMA1_RLC0_IB_CNTL_DEFAULT                    0x0100
#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT                  0x0000
#define mmSDMA1_RLC0_IB_RPTR_DEFAULT                    0x0000
#define mmSDMA1_RLC0_IB_SIZE_DEFAULT                    0x0000
#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT              0x0000
#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT                0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT               0x0000
#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT               0x0000
#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT           0x0000
#define mmSDMA1_RLC0_PREEMPT_DEFAULT                    0x0000
#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT                0x4000
#define mmSDMA1_RLC0_RB_BASE_DEFAULT                    0x0000
#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT            0x0000
#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT            0x0000
#define mmSDMA1_RLC0_RB_RPTR_DEFAULT                    0x0000
#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC0_RB_WPTR_DEFAULT                    0x0000
#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT       0x0000
#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT       0x0000
#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT          0x401000
#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT                  0x0000
#define mmSDMA1_RLC0_STATUS_DEFAULT                     0x0000
#define mmSDMA1_RLC0_WATERMARK_DEFAULT                  0x0000
#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT             0x0004
#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT                0x0000
#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT                0x0000
#define mmSDMA1_RLC1_DOORBELL_DEFAULT                   0x0000
#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT               0x0000
#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT            0x0000
#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT                  0x000F
#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT                 0x0000
#define mmSDMA1_RLC1_IB_CNTL_DEFAULT                    0x0100
#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT                  0x0000
#define mmSDMA1_RLC1_IB_RPTR_DEFAULT                    0x0000
#define mmSDMA1_RLC1_IB_SIZE_DEFAULT                    0x0000
#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT              0x0000
#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT                0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT               0x0000
#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT               0x0000
#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT           0x0000
#define mmSDMA1_RLC1_PREEMPT_DEFAULT                    0x0000
#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT                0x4000
#define mmSDMA1_RLC1_RB_BASE_DEFAULT                    0x0000
#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT            0x0000
#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT            0x0000
#define mmSDMA1_RLC1_RB_RPTR_DEFAULT                    0x0000
#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC1_RB_WPTR_DEFAULT                    0x0000
#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT                 0x0000
#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT       0x0000
#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT       0x0000
#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT          0x401000
#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT                  0x0000
#define mmSDMA1_RLC1_STATUS_DEFAULT                     0x0000
#define mmSDMA1_RLC1_WATERMARK_DEFAULT                  0x0000
#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT        0x0000
#define mmSDMA1_STATUS1_REG_DEFAULT                     0x03FF
#define mmSDMA1_STATUS2_REG_DEFAULT                     0x0001
#define mmSDMA1_STATUS_REG_DEFAULT                      0x46DEE557
#define mmSDMA1_UCODE_ADDR_DEFAULT                      0x0000
#define mmSDMA1_UCODE_CHECKSUM_DEFAULT                  0x0000
#define mmSDMA1_UCODE_DATA_DEFAULT                      0x0000
#define mmSDMA1_ULV_CNTL_DEFAULT__GFX09                 0x0000
#define mmSDMA1_UNBREAKABLE_DEFAULT                     0x0000
#define mmSDMA1_UTCL1_INV1_DEFAULT                      0x0000
#define mmSDMA1_UTCL1_INV2_DEFAULT                      0x0000
#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT                 0x0000
#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT                 0x0000
#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT                 0x0000
#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT                 0x0000
#define mmSDMA1_VF_ENABLE_DEFAULT                       0x0000
#define mmSDMA1_VIRT_RESET_REQ_DEFAULT                  0x0000
#define mmSDMA1_VM_CNTL_DEFAULT                         0x0000
#define mmSDMA1_VM_CTX_HI_DEFAULT                       0x0000
#define mmSDMA1_VM_CTX_LO_DEFAULT                       0x0000
#define mmSDMA_PGFSM_CONFIG_DEFAULT                     0x0000
#define mmSDMA_PGFSM_READ_DEFAULT                       0x0000
#define mmSDMA_PGFSM_WRITE_DEFAULT                      0x0000
#define mmSDMA_POWER_GATING_DEFAULT                     0x0000
#define mmSEM_ACTIVE_FCN_ID_DEFAULT                     0x0000
#define mmSEM_ATOMIC_OP_LUT_DEFAULT                     0x40A102F
#define mmSEM_CHICKEN_BITS2_DEFAULT                     0x0000
#define mmSEM_CID_REMAP_DATA_DEFAULT                    0x0000
#define mmSEM_CID_REMAP_INDEX_DEFAULT                   0x0000
#define mmSEM_CLK_CTRL_DEFAULT                          0x0100
#define mmSEM_EDC_CONFIG_DEFAULT                        0x0002
#define mmSEM_GPU_IOV_VIOLATION_LOG_DEFAULT             0x0000
#define mmSEM_MAILBOX_CLIENTCONFIG_DEFAULT              0xFAC688
#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_DEFAULT        0x0008
#define mmSEM_MAILBOX_CONTROL_DEFAULT                   0x0000
#define mmSEM_MAILBOX_DEFAULT                           0x0000
#define mmSEM_MCIF_CONFIG_DEFAULT                       0x1040
#define mmSEM_OUTSTANDING_THRESHOLD_DEFAULT             0x0010
#define mmSEM_PERFCOUNTER0_RESULT_DEFAULT               0x0000
#define mmSEM_PERFCOUNTER1_RESULT_DEFAULT               0x0000
#define mmSEM_PERFMON_CNTL_DEFAULT                      0x0000
#define mmSEM_REGISTER_LAST_PART0_DEFAULT               0x0000
#define mmSEM_REGISTER_LAST_PART1_DEFAULT               0x0000
#define mmSEM_REGISTER_LAST_PART2_DEFAULT               0x0000
#define mmSEM_REQ_INPUT_0_DEFAULT                       0x0000
#define mmSEM_REQ_INPUT_1_DEFAULT                       0x0000
#define mmSEM_REQ_INPUT_2_DEFAULT                       0x0000
#define mmSEM_REQ_INPUT_3_DEFAULT                       0x0000
#define mmSEM_RESP_ISP_DEFAULT                          0x0000
#define mmSEM_RESP_VP8_DEFAULT                          0x0000
#define mmSEM_STATUS_DEFAULT                            0x80F90003
#define mmSEM_UTCL2_TRAN_EN_LUT_DEFAULT                 0x800000FF
#define mmSEM_UTC_CONFIG_DEFAULT                        0x0020
#define mmSEM_UTC_CREDIT_DEFAULT                        0x0510
#define mmSEM_VIRT_RESET_REQ_DEFAULT                    0x0000
#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT                  0x0100
#define mmSE_CAC_IND_DATA_DEFAULT                       0x0000
#define mmSE_CAC_IND_INDEX_DEFAULT                      0x0000
#define mmSH_MEM_BASES_DEFAULT                          0x0000
#define mmSH_MEM_CONFIG_DEFAULT                         0x0000
#define mmSMU_RLC_RESPONSE_DEFAULT                      0x0000
#define mmSPIS_DEBUG_READ_DEFAULT                       0xCDCDCDCD
#define mmSPI_ARB_CNTL_0_DEFAULT                        0x0000
#define mmSPI_ARB_CYCLES_0_DEFAULT                      0x0000
#define mmSPI_ARB_CYCLES_1_DEFAULT                      0x0000
#define mmSPI_ARB_PRIORITY_DEFAULT                      0x0000
#define mmSPI_BARYC_CNTL_DEFAULT                        0x1010101
#define mmSPI_CDBG_SYS_CS0_DEFAULT                      0x0000
#define mmSPI_CDBG_SYS_CS1_DEFAULT                      0x0000
#define mmSPI_CDBG_SYS_GFX_DEFAULT                      0x0000
#define mmSPI_CDBG_SYS_HP3D_DEFAULT                     0x0000
#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT               0x0001
#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT               0x0000
#define mmSPI_CONFIG_CNTL_2_DEFAULT                     0x0011
#define mmSPI_CONFIG_PS_CU_EN_DEFAULT__GFX09            0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT             0x0000
#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT              0x0000
#define mmSPI_DEBUG_READ_DEFAULT                        0xCDCDCDCD
#define mmSPI_DSM_CNTL2_DEFAULT                         0x0000
#define mmSPI_DSM_CNTL_DEFAULT                          0x0000
#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT                  0x0000
#define mmSPI_GDBG_TRAP_DATA0_DEFAULT                   0x0000
#define mmSPI_GDBG_TRAP_DATA1_DEFAULT                   0x0000
#define mmSPI_GDBG_TRAP_MASK_DEFAULT                    0x0000
#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT                   0x0000
#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT                   0x0000
#define mmSPI_GDBG_WAVE_CNTL_DEFAULT                    0x0000
#define mmSPI_GFX_CNTL_DEFAULT                          0x0000
#define mmSPI_INTERP_CONTROL_0_DEFAULT                  0x4DCD
#define mmSPI_LB_CTR_CTRL_DEFAULT                       0x0000
#define mmSPI_LB_CU_MASK_DEFAULT__GFX09                 0xFFFF
#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT__GFX09      0x0000
#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT__GFX09    0x0000
#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT__GFX09    0x0000
#define mmSPI_LB_DATA_REG_DEFAULT                       0x0000
#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT            0x0000
#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT            0x0000
#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT            0x0000
#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT            0x0000
#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT            0x0000
#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT            0x0000
#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT            0x0000
#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT            0x0000
#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT            0x0000
#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT            0x0000
#define mmSPI_PERFCOUNTER0_HI_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER0_LO_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT              0xFFFFF
#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT               0xFFFFF
#define mmSPI_PERFCOUNTER1_HI_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER1_LO_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT              0xFFFFF
#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT               0xFFFFF
#define mmSPI_PERFCOUNTER2_HI_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER2_LO_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT              0xFFFFF
#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT               0xFFFFF
#define mmSPI_PERFCOUNTER3_HI_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER3_LO_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT              0xFFFFF
#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT               0xFFFFF
#define mmSPI_PERFCOUNTER4_HI_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER4_LO_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER5_HI_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER5_LO_DEFAULT                   0xCDCDCDCD
#define mmSPI_PERFCOUNTER_BINS_DEFAULT                  0xFCB87430
#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT__GFX09   0xFFFF
#define mmSPI_PS_INPUT_ADDR_DEFAULT                     0xCDCD
#define mmSPI_PS_INPUT_CNTL_0_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_10_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_11_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_12_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_13_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_14_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_15_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_16_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_17_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_18_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_19_DEFAULT                  0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_1_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_20_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_21_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_22_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_23_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_24_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_25_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_26_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_27_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_28_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_29_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_2_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_30_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_31_DEFAULT                  0x14C050D
#define mmSPI_PS_INPUT_CNTL_3_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_4_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_5_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_6_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_7_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_8_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_CNTL_9_DEFAULT                   0x1CDC50D
#define mmSPI_PS_INPUT_ENA_DEFAULT                      0xCDCD
#define mmSPI_RESET_DEBUG_DEFAULT                       0x0000
#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT            0x0000
#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT            0x0000
#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT            0x0000
#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT            0x0000
#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT            0x0000
#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT            0x0000
#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT             0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT         0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT         0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT         0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT         0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT         0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT         0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT          0x0000
#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT          0x0000
#define mmSPI_SHADER_COL_FORMAT_DEFAULT                 0xCDCDCDCD
#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT              0x000D
#define mmSPI_SHADER_PGM_HI_ES_DEFAULT                  0x00CD
#define mmSPI_SHADER_PGM_HI_GS_DEFAULT                  0x00CD
#define mmSPI_SHADER_PGM_HI_HS_DEFAULT                  0x00CD
#define mmSPI_SHADER_PGM_HI_LS_DEFAULT                  0x00CD
#define mmSPI_SHADER_PGM_HI_PS_DEFAULT                  0x00CD
#define mmSPI_SHADER_PGM_HI_VS_DEFAULT                  0x00CD
#define mmSPI_SHADER_PGM_LO_ES_DEFAULT                  0xCDCDCDCD
#define mmSPI_SHADER_PGM_LO_GS_DEFAULT                  0xCDCDCDCD
#define mmSPI_SHADER_PGM_LO_HS_DEFAULT                  0xCDCDCDCD
#define mmSPI_SHADER_PGM_LO_LS_DEFAULT                  0xCDCDCDCD
#define mmSPI_SHADER_PGM_LO_PS_DEFAULT                  0xCDCDCDCD
#define mmSPI_SHADER_PGM_LO_VS_DEFAULT                  0xCDCDCDCD
#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT               0xDCDCDCD
#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT            0xDCDCDCD
#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT               0xDCDCDCD
#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT               0x94DCDCD
#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT               0xFFFE
#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT               0xFFFF0000
#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT               0xFFFF
#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT               0xFFFF
#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT       0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT       0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT       0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT       0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT__GFX09 0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT__GFX09  0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT__GFX09     0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT            0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT             0xCDCDCDCD
#define mmSPI_SHADER_Z_FORMAT_DEFAULT                   0x000D
#define mmSPI_START_PHASE_DEFAULT                       0x0000
#define mmSPI_TMPRING_SIZE_DEFAULT                      0x1CDCDCD
#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT              0x007F
#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT              0x7FFFFFF
#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT             0x7C1F07F
#define mmSPI_WF_LIFETIME_CNTL_DEFAULT                  0x0000
#define mmSPI_WF_LIFETIME_DEBUG_DEFAULT                 0x0000
#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT               0x0100
#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT             0x0000
#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT              0x0000
#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT              0x0000
#define mmSQC_CACHES_DEFAULT                            0x0000
#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT__GFX09         0x0500
#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT__GFX09         0x0000
#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT__GFX09        0x0000
#define mmSQC_DSM_CNTL2A_DEFAULT__GFX09                 0x0000
#define mmSQC_DSM_CNTL2B_DEFAULT__GFX09                 0x0000
#define mmSQC_DSM_CNTL2_DEFAULT__GFX09                  0x0000
#define mmSQC_DSM_CNTLA_DEFAULT__GFX09                  0x0000
#define mmSQC_DSM_CNTLB_DEFAULT__GFX09                  0x0000
#define mmSQC_DSM_CNTL_DEFAULT__GFX09                   0x0000
#define mmSQC_EDC_CNT2_DEFAULT__GFX09                   0x0000
#define mmSQC_EDC_CNT3_DEFAULT__GFX09                   0x0000
#define mmSQC_EDC_CNT_DEFAULT__GFX09                    0x0000
#define mmSQC_EDC_FUE_CNTL_DEFAULT__GFX09               0x0000
#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT__GFX09         0x0480
#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT__GFX09         0x0000
#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT__GFX09        0x0000
#define mmSQC_WRITEBACK_DEFAULT                         0x0000
#define mmSQ_ALU_CLK_CTRL_DEFAULT                       0x0000
#define mmSQ_BUF_RSRC_WORD0_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_BUF_RSRC_WORD1_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_BUF_RSRC_WORD2_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_BUF_RSRC_WORD3_DEFAULT__GFX09              0xC8CDCDCD
#define mmSQ_CMD_TIMESTAMP_DEFAULT__GFX09               0x0000
#define mmSQ_CONFIG_DEFAULT                             0x1180000
#define mmSQ_DSM_CNTL2_DEFAULT                          0x0000
#define mmSQ_DSM_CNTL_DEFAULT                           0x0000
#define mmSQ_DS_0_DEFAULT__GFX09                        0x0000
#define mmSQ_DS_1_DEFAULT__GFX09                        0x0000
#define mmSQ_EDC_CNT_DEFAULT                            0x0000
#define mmSQ_EDC_DED_CNT_DEFAULT__GFX09                 0x0000
#define mmSQ_EDC_FUE_CNTL_DEFAULT                       0x0000
#define mmSQ_EDC_INFO_DEFAULT__GFX09                    0x0000
#define mmSQ_EDC_SEC_CNT_DEFAULT__GFX09                 0x0000
#define mmSQ_EXP_0_DEFAULT__GFX09                       0x0000
#define mmSQ_EXP_1_DEFAULT__GFX09                       0x0000
#define mmSQ_FLAT_0_DEFAULT__GFX09                      0x0000
#define mmSQ_FLAT_1_DEFAULT__GFX09                      0x0000
#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT__GFX09          0x5CDCD
#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT__GFX09          0xCDCDCD
#define mmSQ_GLBL_0_DEFAULT__GFX09                      0x0000
#define mmSQ_GLBL_1_DEFAULT__GFX09                      0x0000
#define mmSQ_IMG_RSRC_WORD0_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_RSRC_WORD1_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_RSRC_WORD2_DEFAULT__GFX09              0x4DCDCDCD
#define mmSQ_IMG_RSRC_WORD3_DEFAULT__GFX09              0xC1CDCDCD
#define mmSQ_IMG_RSRC_WORD4_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_RSRC_WORD5_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_RSRC_WORD6_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_RSRC_WORD7_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_SAMP_WORD0_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_SAMP_WORD1_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_SAMP_WORD2_DEFAULT__GFX09              0xCDCDCDCD
#define mmSQ_IMG_SAMP_WORD3_DEFAULT__GFX09              0xC0000DCD
#define mmSQ_IND_DATA_DEFAULT                           0xCDCDCDCD
#define mmSQ_IND_INDEX_DEFAULT                          0x0000
#define mmSQ_INST_DEFAULT__GFX09                        0x0000
#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT                0xFFFFFF
#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT                 0x0000
#define mmSQ_LB_CTR0_CU_DEFAULT__GFX09                  0xFFFFFFFF
#define mmSQ_LB_CTR1_CU_DEFAULT__GFX09                  0xFFFFFFFF
#define mmSQ_LB_CTR2_CU_DEFAULT__GFX09                  0xFFFFFFFF
#define mmSQ_LB_CTR3_CU_DEFAULT__GFX09                  0xFFFFFFFF
#define mmSQ_LB_CTR_CTRL_DEFAULT                        0x0000
#define mmSQ_LB_CTR_SEL_DEFAULT__GFX09                  0x0000
#define mmSQ_LB_DATA0_DEFAULT                           0x0000
#define mmSQ_LB_DATA1_DEFAULT                           0x0000
#define mmSQ_LB_DATA2_DEFAULT                           0x0000
#define mmSQ_LB_DATA3_DEFAULT                           0x0000
#define mmSQ_LDS_CLK_CTRL_DEFAULT                       0x0000
#define mmSQ_M0_GPR_IDX_WORD_DEFAULT__GFX09             0xC0CD
#define mmSQ_MIMG_0_DEFAULT__GFX09                      0x0000
#define mmSQ_MIMG_1_DEFAULT__GFX09                      0x0000
#define mmSQ_MTBUF_0_DEFAULT__GFX09                     0x0000
#define mmSQ_MTBUF_1_DEFAULT__GFX09                     0x0000
#define mmSQ_MUBUF_0_DEFAULT__GFX09                     0x0000
#define mmSQ_MUBUF_1_DEFAULT__GFX09                     0x0000
#define mmSQ_PERFCOUNTER0_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER0_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER10_HI_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER10_LO_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER11_HI_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER11_LO_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER12_HI_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER12_LO_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER13_HI_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER13_LO_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER14_HI_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER14_LO_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER15_HI_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER15_LO_DEFAULT                   0xCDCDCDCD
#define mmSQ_PERFCOUNTER1_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER1_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER2_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER2_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER3_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER3_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER4_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER4_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER5_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER5_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER6_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER6_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER7_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER7_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER8_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER8_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER9_HI_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER9_LO_DEFAULT                    0xCDCDCDCD
#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT                  0x0000
#define mmSQ_PERFCOUNTER_MASK_DEFAULT__GFX09            0xFFFFFFFF
#define mmSQ_POWER_THROTTLE2_DEFAULT__GFX09             0x18800004
#define mmSQ_POWER_THROTTLE_DEFAULT__GFX09              0x3FFF3FFF
#define mmSQ_RANDOM_WAVE_PRI_DEFAULT                    0x007F
#define mmSQ_REG_CREDITS_DEFAULT__GFX09                 0x0820
#define mmSQ_REG_TIMESTAMP_DEFAULT__GFX09               0x0000
#define mmSQ_RUNTIME_CONFIG_DEFAULT                     0x0000
#define mmSQ_SCRATCH_0_DEFAULT__GFX09                   0x0000
#define mmSQ_SCRATCH_1_DEFAULT__GFX09                   0x0000
#define mmSQ_SHADER_TBA_HI_DEFAULT                      0x0000
#define mmSQ_SHADER_TBA_LO_DEFAULT                      0x0000
#define mmSQ_SHADER_TMA_HI_DEFAULT                      0x0000
#define mmSQ_SHADER_TMA_LO_DEFAULT                      0x0000
#define mmSQ_SMEM_0_DEFAULT__GFX09                      0x0000
#define mmSQ_SMEM_1_DEFAULT__GFX09                      0x0000
#define mmSQ_SOP1_DEFAULT__GFX09                        0x0000
#define mmSQ_SOP2_DEFAULT__GFX09                        0x0000
#define mmSQ_SOPC_DEFAULT__GFX09                        0x0000
#define mmSQ_SOPK_DEFAULT__GFX09                        0x0000
#define mmSQ_SOPP_DEFAULT__GFX09                        0x0000
#define mmSQ_TEX_CLK_CTRL_DEFAULT                       0x0000
#define mmSQ_THREAD_TRACE_BASE2_DEFAULT__GFX09          0x0000
#define mmSQ_THREAD_TRACE_BASE_DEFAULT__GFX09           0x0000
#define mmSQ_THREAD_TRACE_CNTR_DEFAULT__GFX09           0x0000
#define mmSQ_THREAD_TRACE_CTRL_DEFAULT                  0x0000
#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT__GFX09        0x0000
#define mmSQ_THREAD_TRACE_MODE_DEFAULT__GFX09           0x2049249
#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT__GFX09      0xFFFFFFFF
#define mmSQ_THREAD_TRACE_SIZE_DEFAULT__GFX09           0x0000
#define mmSQ_THREAD_TRACE_STATUS_DEFAULT                0x0000
#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT__GFX09    0xFFFFFFFF
#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT            0xCDCDCDCD
#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT            0xCDCDCDCD
#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT            0xCDCDCDCD
#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT            0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT__GFX09       0x000D
#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT__GFX09     0xCDCD
#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT__GFX09      0xCDCD
#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT__GFX09 0xCDCD85CD
#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT__GFX09 0xCDCDCD
#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT__GFX09 0xCDCD
#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT__GFX09     0xDCDCD4D
#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT__GFX09      0xCDCD
#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT__GFX09 0xCDCD
#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT__GFX09 0xCDCD000D
#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT__GFX09      0xCDCD
#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT__GFX09 0xCDCDCDCD
#define mmSQ_TIME_HI_DEFAULT                            0x0000
#define mmSQ_TIME_LO_DEFAULT                            0x0000
#define mmSQ_UTCL1_CNTL1_DEFAULT__GFX09                 0x0580
#define mmSQ_UTCL1_CNTL2_DEFAULT__GFX09                 0x0000
#define mmSQ_UTCL1_STATUS_DEFAULT__GFX09                0x0000
#define mmSQ_VINTRP_DEFAULT__GFX09                      0x0000
#define mmSQ_VOP1_DEFAULT__GFX09                        0x0000
#define mmSQ_VOP2_DEFAULT__GFX09                        0x0000
#define mmSQ_VOP3P_0_DEFAULT__GFX09                     0x0000
#define mmSQ_VOP3P_1_DEFAULT__GFX09                     0x0000
#define mmSQ_VOP3_0_DEFAULT__GFX09                      0x0000
#define mmSQ_VOP3_0_SDST_ENC_DEFAULT__GFX09             0x0000
#define mmSQ_VOP3_1_DEFAULT__GFX09                      0x0000
#define mmSQ_VOPC_DEFAULT__GFX09                        0x0000
#define mmSQ_VOP_DPP_DEFAULT__GFX09                     0x0000
#define mmSQ_VOP_SDWA_DEFAULT__GFX09                    0x0000
#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT__GFX09           0x0000
#define mmSQ_WREXEC_EXEC_LO_DEFAULT                     0xCDCDCDCD
#define mmSX_BLEND_OPT_CONTROL_DEFAULT                  0x81010101
#define mmSX_BLEND_OPT_EPSILON_DEFAULT                  0xCDCDCDCD
#define mmSX_DEBUG_1_DEFAULT                            0x0020
#define mmSX_DEBUG_BUSY_2_DEFAULT                       0xCDCDCDCD
#define mmSX_DEBUG_BUSY_3_DEFAULT                       0xCDCDCDCD
#define mmSX_DEBUG_BUSY_4_DEFAULT                       0xCDCDCDCD
#define mmSX_DEBUG_BUSY_5_DEFAULT                       0xCDCDCDCD
#define mmSX_DEBUG_BUSY_DEFAULT                         0xCDCDCDCD
#define mmSX_MRT0_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT1_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT2_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT3_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT4_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT5_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT6_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_MRT7_BLEND_OPT_DEFAULT                     0x5450545
#define mmSX_PERFCOUNTER0_HI_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER0_LO_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT               0xDCDCD
#define mmSX_PERFCOUNTER0_SELECT_DEFAULT                0xCDCDCD
#define mmSX_PERFCOUNTER1_HI_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER1_LO_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT               0xDCDCD
#define mmSX_PERFCOUNTER1_SELECT_DEFAULT                0xCDCDCD
#define mmSX_PERFCOUNTER2_HI_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER2_LO_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER2_SELECT_DEFAULT                0xCDCDCD
#define mmSX_PERFCOUNTER3_HI_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER3_LO_DEFAULT                    0xCDCDCDCD
#define mmSX_PERFCOUNTER3_SELECT_DEFAULT                0xCDCDCD
#define mmSX_PS_DOWNCONVERT_DEFAULT                     0xCDCDCDCD
#define mmTA_BC_BASE_ADDR_DEFAULT                       0xCDCDCDCD
#define mmTA_BC_BASE_ADDR_HI_DEFAULT                    0x00CD
#define mmTA_CGTT_CTRL_DEFAULT                          0x0100
#define mmTA_CS_BC_BASE_ADDR_DEFAULT                    0xCDCDCDCD
#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT                 0x00CD
#define mmTA_PERFCOUNTER0_HI_DEFAULT                    0xCDCDCDCD
#define mmTA_PERFCOUNTER0_LO_DEFAULT                    0xCDCDCDCD
#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT               0x0000
#define mmTA_PERFCOUNTER0_SELECT_DEFAULT                0x1CCCD
#define mmTA_PERFCOUNTER1_HI_DEFAULT                    0xCDCDCDCD
#define mmTA_PERFCOUNTER1_LO_DEFAULT                    0xCDCDCDCD
#define mmTA_RESERVED_010C_DEFAULT                      0x0000
#define mmTA_SCRATCH_DEFAULT                            0x0000
#define mmTA_STATUS_DEFAULT                             0xCD454000
#define mmTCA_BURST_CTRL_DEFAULT__GFX09                 0x0007
#define mmTCA_BURST_MASK_DEFAULT__GFX09                 0xFFFFFFFF
#define mmTCA_CGTT_SCLK_CTRL_DEFAULT__GFX09             0x0100
#define mmTCA_CTRL_DEFAULT__GFX09                       0x0088
#define mmTCA_DSM_CNTL2_DEFAULT__GFX09                  0x0000
#define mmTCA_DSM_CNTL_DEFAULT__GFX09                   0x0000
#define mmTCA_EDC_CNT_DEFAULT__GFX09                    0x0000
#define mmTCA_PERFCOUNTER0_HI_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER0_LO_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0xFFFFF
#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0xFFFFF
#define mmTCA_PERFCOUNTER1_HI_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER1_LO_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT__GFX09       0xFFFFF
#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0xFFFFF
#define mmTCA_PERFCOUNTER2_HI_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER2_LO_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT__GFX09        0x03FF
#define mmTCA_PERFCOUNTER3_HI_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER3_LO_DEFAULT__GFX09            0x0000
#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT__GFX09        0x03FF
#define mmTCC_CGTT_SCLK_CTRL_DEFAULT__GFX09             0x0100
#define mmTCC_CTRL2_DEFAULT__GFX09                      0x000F
#define mmTCC_CTRL_DEFAULT__GFX09                       0xF30FFF7F
#define mmTCC_DSM_CNTL2A_DEFAULT__GFX09                 0x0000
#define mmTCC_DSM_CNTL2B_DEFAULT__GFX09                 0x0000
#define mmTCC_DSM_CNTL2_DEFAULT__GFX09                  0x0000
#define mmTCC_DSM_CNTLA_DEFAULT__GFX09                  0x0000
#define mmTCC_DSM_CNTL_DEFAULT__GFX09                   0x0000
#define mmTCC_EDC_CNT2_DEFAULT__GFX09                   0x0000
#define mmTCC_EDC_CNT_DEFAULT__GFX09                    0x0000
#define mmTCC_EXE_DISABLE_DEFAULT__GFX09                0x0000
#define mmTCC_PERFCOUNTER0_HI_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER0_LO_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0xFFFFF
#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0xFFFFF
#define mmTCC_PERFCOUNTER1_HI_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER1_LO_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT__GFX09       0xFFFFF
#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0xFFFFF
#define mmTCC_PERFCOUNTER2_HI_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER2_LO_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT__GFX09        0x03FF
#define mmTCC_PERFCOUNTER3_HI_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER3_LO_DEFAULT__GFX09            0x0000
#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT__GFX09        0x03FF
#define mmTCC_REDUNDANCY_DEFAULT__GFX09                 0x0000
#define mmTCC_SOFT_RESET_DEFAULT__GFX09                 0x0000
#define mmTCC_WBINVL2_DEFAULT__GFX09                    0x0010
#define mmTCI_CNTL_1_DEFAULT                            0x40080022
#define mmTCI_CNTL_2_DEFAULT                            0x0041
#define mmTCI_STATUS_DEFAULT                            0x0001
#define mmTCP_ADDR_CONFIG_DEFAULT__GFX09                0x00FF
#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT__GFX09         0x0000
#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT             0x0000
#define mmTCP_CHAN_STEER_HI_DEFAULT__GFX09              0xFEDCBA98
#define mmTCP_CHAN_STEER_LO_DEFAULT__GFX09              0x76543210
#define mmTCP_CNTL2_DEFAULT                             0x000A
#define mmTCP_EDC_CNT_DEFAULT                           0x0000
#define mmTCP_GATCL1_CNTL_DEFAULT__GFX09                0x0000
#define mmTCP_GATCL1_DSM_CNTL_DEFAULT__GFX09            0x0000
#define mmTCP_INVALIDATE_DEFAULT                        0x0000
#define mmTCP_PERFCOUNTER0_HI_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER0_LO_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT              0xFFFFF
#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT               0xFFFFF
#define mmTCP_PERFCOUNTER1_HI_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER1_LO_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT              0xFFFFF
#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT               0xFFFFF
#define mmTCP_PERFCOUNTER2_HI_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER2_LO_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT               0x03FF
#define mmTCP_PERFCOUNTER3_HI_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER3_LO_DEFAULT                   0x0000
#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT               0x03FF
#define mmTCP_PERFCOUNTER_FILTER_DEFAULT                0x4DCDCDCD
#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT             0x0000
#define mmTCP_UTCL1_CNTL1_DEFAULT__GFX09                0x800400
#define mmTCP_UTCL1_CNTL2_DEFAULT__GFX09                0x0000
#define mmTCP_UTCL1_STATUS_DEFAULT__GFX09               0x0000
#define mmTCP_WATCH0_ADDR_H_DEFAULT                     0x0000
#define mmTCP_WATCH0_ADDR_L_DEFAULT                     0x0000
#define mmTCP_WATCH0_CNTL_DEFAULT                       0x40000000
#define mmTCP_WATCH1_ADDR_H_DEFAULT                     0x0000
#define mmTCP_WATCH1_ADDR_L_DEFAULT                     0x0000
#define mmTCP_WATCH1_CNTL_DEFAULT                       0x40000000
#define mmTCP_WATCH2_ADDR_H_DEFAULT                     0x0000
#define mmTCP_WATCH2_ADDR_L_DEFAULT                     0x0000
#define mmTCP_WATCH2_CNTL_DEFAULT                       0x40000000
#define mmTCP_WATCH3_ADDR_H_DEFAULT                     0x0000
#define mmTCP_WATCH3_ADDR_L_DEFAULT                     0x0000
#define mmTCP_WATCH3_CNTL_DEFAULT                       0x40000000
#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT__GFX09         0xCDCDCDCD
#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT__GFX09         0xCDCDCDCD
#define mmTC_CFG_L1_STORE_POLICY_DEFAULT__GFX09         0xCDCDCDCD
#define mmTC_CFG_L1_VOLATILE_DEFAULT__GFX09             0x000D
#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT__GFX09        0xCDCDCDCD
#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT__GFX09         0xCDCDCDCD
#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT__GFX09         0xCDCDCDCD
#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT__GFX09        0xCDCDCDCD
#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT__GFX09        0xCDCDCDCD
#define mmTC_CFG_L2_VOLATILE_DEFAULT__GFX09             0x000D
#define mmTD_CGTT_CTRL_DEFAULT                          0x0100
#define mmTD_CNTL_DEFAULT                               0x0000
#define mmTD_DSM_CNTL2_DEFAULT                          0x0000
#define mmTD_DSM_CNTL_DEFAULT                           0x0000
#define mmTD_PERFCOUNTER0_HI_DEFAULT                    0xCDCDCDCD
#define mmTD_PERFCOUNTER0_LO_DEFAULT                    0xCDCDCDCD
#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT               0x1CCCD
#define mmTD_PERFCOUNTER0_SELECT_DEFAULT                0x1CCCD
#define mmTD_PERFCOUNTER1_HI_DEFAULT                    0xCDCDCDCD
#define mmTD_PERFCOUNTER1_LO_DEFAULT                    0xCDCDCDCD
#define mmTD_SCRATCH_DEFAULT                            0x0000
#define mmTD_STATUS_DEFAULT                             0x80000000
#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT__GFX09            0x0080
#define mmVGT_CACHE_INVALIDATION_DEFAULT                0x9000000
#define mmVGT_CNTL_STATUS_DEFAULT                       0x05CD
#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT               0xCDCDCDCD
#define mmVGT_DMA_BASE_DEFAULT                          0xCDCDCDCD
#define mmVGT_DMA_BASE_HI_DEFAULT                       0xCDCD
#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT               0xDCDCC0D
#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT                  0x0D00
#define mmVGT_DMA_MAX_SIZE_DEFAULT                      0xCDCDCDCD
#define mmVGT_DMA_NUM_INSTANCES_DEFAULT                 0xCDCDCDCD
#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT                0x000D
#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT                0x0020
#define mmVGT_DMA_SIZE_DEFAULT                          0xCDCDCDCD
#define mmVGT_DRAW_INITIATOR_DEFAULT                    0xC00001CD
#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT              0x0020
#define mmVGT_ENHANCE_DEFAULT                           0xCDCDCDCD
#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT                0x4DCD
#define mmVGT_ES_PER_GS_DEFAULT                         0x05CD
#define mmVGT_EVENT_ADDRESS_REG_DEFAULT                 0xDCDCDCD
#define mmVGT_EVENT_INITIATOR_DEFAULT                   0xDCDCC0D
#define mmVGT_GROUP_DECR_DEFAULT                        0x000D
#define mmVGT_GROUP_FIRST_DECR_DEFAULT                  0x000D
#define mmVGT_GROUP_PRIM_TYPE_DEFAULT                   0x5C00D
#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT                 0xCDCD0D
#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT             0xCDCDCDCD
#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT                 0xCDCD0D
#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT             0xCDCDCDCD
#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT                0x4DCD
#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT                0x4DCD
#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT                0x4DCD
#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT                0x4DCD
#define mmVGT_GSVS_RING_SIZE_DEFAULT                    0x0000
#define mmVGT_GS_INSTANCE_CNT_DEFAULT                   0x01CD
#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT__GFX09  0x0000
#define mmVGT_GS_MAX_VERT_OUT_DEFAULT                   0x05CD
#define mmVGT_GS_MAX_WAVE_ID_DEFAULT                    0x03FF
#define mmVGT_GS_MODE_DEFAULT                           0x4DCDCD
#define mmVGT_GS_ONCHIP_CNTL_DEFAULT                    0xCDCDCDCD
#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT                  0x0000
#define mmVGT_GS_PER_ES_DEFAULT                         0x05CD
#define mmVGT_GS_PER_VS_DEFAULT                         0x000D
#define mmVGT_GS_VERTEX_REUSE_DEFAULT                   0x0010
#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT                0x4DCD
#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT                0x4DCD
#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT                0x4DCD
#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT                  0x4DCD
#define mmVGT_HOS_CNTL_DEFAULT                          0x0001
#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT                0xCDCDCDCD
#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT                0xCDCDCDCD
#define mmVGT_HOS_REUSE_DEPTH_DEFAULT                   0x00CD
#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT                  0x0000
#define mmVGT_IMMED_DATA_DEFAULT                        0xCDCDCDCD
#define mmVGT_INDX_OFFSET_DEFAULT                       0xCDCDCDCD
#define mmVGT_INSTANCE_BASE_ID_DEFAULT                  0x0000
#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT              0xCDCDCDCD
#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT              0xCDCDCDCD
#define mmVGT_LAST_COPY_STATE_DEFAULT                   0x50005
#define mmVGT_LS_HS_CONFIG_DEFAULT                      0xDCDCD
#define mmVGT_MAX_VTX_INDX_DEFAULT                      0xCDCDCDCD
#define mmVGT_MC_LAT_CNTL_DEFAULT                       0x00FE
#define mmVGT_MIN_VTX_INDX_DEFAULT                      0xCDCDCDCD
#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT            0x0001
#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT          0xCDCDCDCD
#define mmVGT_NUM_INDICES_DEFAULT                       0xCDCDCDCD
#define mmVGT_NUM_INSTANCES_DEFAULT                     0xCDCDCDCD
#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT                  0x0005
#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT                  0x004D
#define mmVGT_PERFCOUNTER0_HI_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER0_LO_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0xDCDCD
#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0xDCDCD
#define mmVGT_PERFCOUNTER1_HI_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER1_LO_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT__GFX09       0xDCDCD
#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0xDCDCD
#define mmVGT_PERFCOUNTER2_HI_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER2_LO_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT__GFX09        0x00CD
#define mmVGT_PERFCOUNTER3_HI_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER3_LO_DEFAULT__GFX09            0xCDCDCDCD
#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT__GFX09        0x00CD
#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT__GFX09      0x0000
#define mmVGT_PRIMITIVEID_EN_DEFAULT                    0x0005
#define mmVGT_PRIMITIVEID_RESET_DEFAULT                 0x0000
#define mmVGT_PRIMITIVE_TYPE_DEFAULT                    0x000D
#define mmVGT_RESET_DEBUG_DEFAULT                       0x0000
#define mmVGT_REUSE_OFF_DEFAULT                         0x0001
#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT             0x0000
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT      0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT      0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT      0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT      0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT           0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT           0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT           0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT           0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT             0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT             0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT             0xCDCDCDCD
#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT             0xCDCDCDCD
#define mmVGT_STRMOUT_CONFIG_DEFAULT                    0x0000
#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0xCDCDCDCD
#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT        0xCDCDCDCD
#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x01CD
#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT              0x01CD
#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT              0x01CD
#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT              0x01CD
#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT              0x01CD
#define mmVGT_SYS_CONFIG_DEFAULT                        0x0011
#define mmVGT_TESS_DISTRIBUTION_DEFAULT                 0xCDCDCDCD
#define mmVGT_TF_MEMORY_BASE_DEFAULT                    0x0000
#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT                 0x0000
#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT           0x00CD
#define mmVGT_VS_MAX_WAVE_ID_DEFAULT                    0x01FF
#define mmVGT_VTX_CNT_EN_DEFAULT                        0x0001
#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT                0x007D
#define mmVM_CONTEXT0_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT10_CNTL_DEFAULT__GFX09              0x7FFE80
#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT11_CNTL_DEFAULT__GFX09              0x7FFE80
#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT12_CNTL_DEFAULT__GFX09              0x7FFE80
#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT13_CNTL_DEFAULT__GFX09              0x7FFE80
#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT14_CNTL_DEFAULT__GFX09              0x7FFE80
#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT15_CNTL_DEFAULT__GFX09              0x7FFE80
#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT1_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT2_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT3_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT4_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT5_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT6_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT7_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT8_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT9_CNTL_DEFAULT__GFX09               0x7FFE80
#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_CONTEXTS_DISABLE_DEFAULT__GFX09            0x0000
#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT__GFX09  0x0000
#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT__GFX09  0x0000
#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT__GFX09       0x0090
#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT__GFX09        0x17C0000
#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT__GFX09        0x0000
#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT__GFX09         0x0000
#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT__GFX09 0x0000
#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT__GFX09         0x17C0000
#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT__GFX09         0x0000
#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT__GFX09      0x0000
#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT__GFX09          0x0100
#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT__GFX09 0x0000
#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT__GFX09 0x0000
#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT__GFX09 0x0000
#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT__GFX09        0x0000
#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT__GFX09            0x0080
#define mmVM_L2_CNTL2_DEFAULT__GFX09                    0x0000
#define mmVM_L2_CNTL3_DEFAULT__GFX09                    0x80100007
#define mmVM_L2_CNTL4_DEFAULT__GFX09                    0x00C1
#define mmVM_L2_CNTL_DEFAULT__GFX09                     0x80602
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT__GFX09 0x0000
#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT__GFX09 0x0000
#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT__GFX09      0x0000
#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT__GFX09   0xA0000
#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT__GFX09    0x3FFFFFFC
#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT__GFX09 0x0000
#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT__GFX09 0x0000
#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT__GFX09 0xFFFFFFFF
#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT__GFX09 0xFFFFFFFF
#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT__GFX09  0x0000
#define mmVM_L2_STATUS_DEFAULT__GFX09                   0x0000
#define mmVM_PCIE_ATS_CNTL_DEFAULT__GFX09               0x0000
#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT__GFX09         0x0000
#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT__GFX09         0x0000
#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT__GFX09         0x0000
#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT__GFX09         0x0000
#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT__GFX09         0x0000
#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT__GFX09         0x0000
#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT__GFX09          0x0000
#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT__GFX09          0x0000
#define mmWD_BUF_RESOURCE_1_DEFAULT                     0x0000
#define mmWD_BUF_RESOURCE_2_DEFAULT                     0x0000
#define mmWD_CNTL_SB_BUF_BASE_DEFAULT                   0x0000
#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT                0x0000
#define mmWD_CNTL_STATUS_DEFAULT                        0x000D
#define mmWD_ENHANCE_DEFAULT                            0xCDCDCDCD
#define mmWD_INDEX_BUF_BASE_DEFAULT                     0x0000
#define mmWD_INDEX_BUF_BASE_HI_DEFAULT                  0x0000
#define mmWD_PERFCOUNTER0_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER0_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER0_SELECT_DEFAULT__GFX09         0x00CD
#define mmWD_PERFCOUNTER1_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER1_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER1_SELECT_DEFAULT__GFX09         0x00CD
#define mmWD_PERFCOUNTER2_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER2_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER2_SELECT_DEFAULT__GFX09         0x00CD
#define mmWD_PERFCOUNTER3_HI_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER3_LO_DEFAULT__GFX09             0xCDCDCDCD
#define mmWD_PERFCOUNTER3_SELECT_DEFAULT__GFX09         0x00CD
#define mmWD_POS_BUF_BASE_DEFAULT                       0x0000
#define mmWD_POS_BUF_BASE_HI_DEFAULT                    0x0000
#define mmWD_QOS_DEFAULT                                0x0000
#define mmWD_UTCL1_CNTL_DEFAULT                         0x0080
#define mmWD_UTCL1_STATUS_DEFAULT                       0x0000
#define mmXPB_CLG_CFG0_DEFAULT                          0x0000
#define mmXPB_CLG_CFG1_DEFAULT                          0x0000
#define mmXPB_CLG_CFG2_DEFAULT                          0x0000
#define mmXPB_CLG_CFG3_DEFAULT                          0x0000
#define mmXPB_CLG_CFG4_DEFAULT                          0x0000
#define mmXPB_CLG_CFG5_DEFAULT                          0x0000
#define mmXPB_CLG_CFG6_DEFAULT                          0x0000
#define mmXPB_CLG_CFG7_DEFAULT                          0x0000
#define mmXPB_CLG_EXTRA_DEFAULT                         0x0000
#define mmXPB_CLG_EXTRA_MSK_DEFAULT                     0x0000
#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT                  0x0000
#define mmXPB_CLG_EXTRA_RD_DEFAULT                      0x0000
#define mmXPB_CLG_GFX_MATCH_DEFAULT                     0x3000000
#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT           0x0000
#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT           0x0040
#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT           0x0080
#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT           0x00C0
#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT           0x0100
#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT           0x0140
#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT           0x0000
#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT           0x01C0
#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT                  0x0000
#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT            0x0000
#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT            0x0040
#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT            0x0080
#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT            0x00C0
#define mmXPB_CLK_GAT_DEFAULT                           0x40400
#define mmXPB_HST_CFG_DEFAULT                           0x0000
#define mmXPB_INTF_CFG2_DEFAULT                         0x0040
#define mmXPB_INTF_CFG_DEFAULT                          0xF1040
#define mmXPB_INTF_STS_DEFAULT                          0x0000
#define mmXPB_LB_ADDR_DEFAULT                           0x0000
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT          0x0000
#define mmXPB_MISC_CFG_DEFAULT                          0x4D585042
#define mmXPB_P2P_BAR0_DEFAULT                          0x0000
#define mmXPB_P2P_BAR1_DEFAULT                          0x0000
#define mmXPB_P2P_BAR2_DEFAULT                          0x0000
#define mmXPB_P2P_BAR3_DEFAULT                          0x0000
#define mmXPB_P2P_BAR4_DEFAULT                          0x0000
#define mmXPB_P2P_BAR5_DEFAULT                          0x0000
#define mmXPB_P2P_BAR6_DEFAULT                          0x0000
#define mmXPB_P2P_BAR7_DEFAULT                          0x0000
#define mmXPB_P2P_BAR_CFG_DEFAULT                       0x000F
#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT               0x0000
#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT               0x0000
#define mmXPB_P2P_BAR_SETUP_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR0_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR1_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR2_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR3_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR4_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR5_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR6_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR7_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR8_DEFAULT                     0x0000
#define mmXPB_PEER_SYS_BAR9_DEFAULT                     0x0000
#define mmXPB_PERF_KNOBS_DEFAULT                        0x0000
#define mmXPB_PIPE_STS_DEFAULT                          0x0000
#define mmXPB_RTR_DEST_MAP0_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP1_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP2_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP3_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP4_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP5_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP6_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP7_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP8_DEFAULT                     0x0000
#define mmXPB_RTR_DEST_MAP9_DEFAULT                     0x0000
#define mmXPB_RTR_SRC_APRTR0_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR1_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR2_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR3_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR4_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR5_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR6_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR7_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR8_DEFAULT                    0x0000
#define mmXPB_RTR_SRC_APRTR9_DEFAULT                    0x0000
#define mmXPB_STICKY_DEFAULT                            0x0000
#define mmXPB_STICKY_W1C_DEFAULT                        0x0000
#define mmXPB_SUB_CTRL_DEFAULT                          0x0000
#define mmXPB_WCB_STS_DEFAULT                           0x0000
#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT                0x0000
#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT                0x0000
#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT                0x0000
#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT                0x0000
#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT                0x0000
#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT                0x0000
#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT                0x0000
#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT                0x0000
#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT               0x0000
#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT               0x0000
#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT               0x0000
#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT               0x0000
#define mmnbif_gpuA2S_CNTL2_SEC_CL0_DEFAULT             0x0006
#define mmnbif_gpuA2S_CNTL2_SEC_CL1_DEFAULT             0x0006
#define mmnbif_gpuA2S_CNTL2_SEC_CL2_DEFAULT__GFX09      0x0006
#define mmnbif_gpuA2S_CNTL2_SEC_CL3_DEFAULT__GFX09      0x0006
#define mmnbif_gpuA2S_CNTL2_SEC_CL4_DEFAULT__GFX09      0x0006
#define mmnbif_gpuA2S_CNTL_CL2_DEFAULT__GFX09           0x2825A0
#define mmnbif_gpuA2S_CNTL_CL3_DEFAULT__GFX09           0x282550
#define mmnbif_gpuA2S_CNTL_CL4_DEFAULT__GFX09           0x282550
#define mmnbif_gpuA2S_MISC_CNTL_DEFAULT                 0x0003
#define mmnbif_gpuADAPTER_ID_W_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuADAPTER_ID_epf_DEFAULT__GFX09         0x0000
#define mmnbif_gpuBACO_CNTL_DEFAULT                     0x0000
#define mmnbif_gpuBASE_ADDR_1_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_ADDR_1_epvf_DEFAULT              0x0000
#define mmnbif_gpuBASE_ADDR_1_swds_DEFAULT              0x0000
#define mmnbif_gpuBASE_ADDR_2_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_ADDR_2_epvf_DEFAULT              0x0000
#define mmnbif_gpuBASE_ADDR_3_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_ADDR_3_epvf_DEFAULT              0x0000
#define mmnbif_gpuBASE_ADDR_4_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_ADDR_4_epvf_DEFAULT              0x0000
#define mmnbif_gpuBASE_ADDR_5_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_ADDR_5_epvf_DEFAULT              0x0000
#define mmnbif_gpuBASE_ADDR_6_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_ADDR_6_epvf_DEFAULT              0x0000
#define mmnbif_gpuBASE_CLASS_epf_DEFAULT__GFX09         0x0000
#define mmnbif_gpuBASE_CLASS_epvf_DEFAULT               0x0000
#define mmnbif_gpuBIFC_BME_ERR_LOG_DEFAULT              0x0000
#define mmnbif_gpuBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x0000
#define mmnbif_gpuBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x0000
#define mmnbif_gpuBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x0000
#define mmnbif_gpuBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x0000
#define mmnbif_gpuBIFC_GSI_CNTL_DEFAULT                 0x17C0
#define mmnbif_gpuBIFC_HSTARB_CNTL_DEFAULT              0x0000
#define mmnbif_gpuBIFC_MISC_CTRL0_DEFAULT               0x8000004
#define mmnbif_gpuBIFC_PCIEFUNC_CNTL_DEFAULT            0x0000
#define mmnbif_gpuBIFC_PERF_CNTL_0_DEFAULT              0x0000
#define mmnbif_gpuBIFC_PERF_CNTL_1_DEFAULT              0x0000
#define mmnbif_gpuBIFC_PERF_CNT_DMA_RD_DEFAULT          0x0000
#define mmnbif_gpuBIFC_PERF_CNT_DMA_WR_DEFAULT          0x0000
#define mmnbif_gpuBIFC_PERF_CNT_MMIO_RD_DEFAULT         0x0000
#define mmnbif_gpuBIFC_PERF_CNT_MMIO_WR_DEFAULT         0x0000
#define mmnbif_gpuBIFC_RCCBIH_BME_ERR_LOG_DEFAULT       0x0000
#define mmnbif_gpuBIFC_SDP_CNTL_0_DEFAULT               0x3F3F3F3F
#define mmnbif_gpuBIFC_SDP_CNTL_1_DEFAULT               0x0000
#define mmnbif_gpuBIFC_THT_CNTL_DEFAULT                 0x0222
#define mmnbif_gpuBIF_ATOMIC_ERR_LOG_DEFAULT            0x0000
#define mmnbif_gpuBIF_BACO_EXIT_TIME0_DEFAULT           0x0100
#define mmnbif_gpuBIF_BACO_EXIT_TIMER1_DEFAULT          0x0200
#define mmnbif_gpuBIF_BACO_EXIT_TIMER2_DEFAULT          0x0300
#define mmnbif_gpuBIF_BACO_EXIT_TIMER3_DEFAULT          0x0500
#define mmnbif_gpuBIF_BACO_EXIT_TIMER4_DEFAULT          0x0400
#define mmnbif_gpuBIF_BME_STATUS_DEFAULT                0x0000
#define mmnbif_gpuBIF_BUSY_DELAY_CNTR_DEFAULT           0x003F
#define mmnbif_gpuBIF_CLKREQB_PAD_CNTL_DEFAULT          0x600100
#define mmnbif_gpuBIF_D3HOTD0_INTR_MASK_DEFAULT         0x00FF
#define mmnbif_gpuBIF_D3HOTD0_INTR_STS_DEFAULT          0x0000
#define mmnbif_gpuBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT     0x0000
#define mmnbif_gpuBIF_DOORBELL_CNTL_DEFAULT             0x0000
#define mmnbif_gpuBIF_DOORBELL_FENCE_CNTL_DEFAULT       0x0000
#define mmnbif_gpuBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT   0x80000780
#define mmnbif_gpuBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT   0x07FC
#define mmnbif_gpuBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT   0x80000800
#define mmnbif_gpuBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT   0x087C
#define mmnbif_gpuBIF_DOORBELL_INT_CNTL_DEFAULT         0x0000
#define mmnbif_gpuBIF_FB_EN_DEFAULT                     0x0000
#define mmnbif_gpuBIF_FEATURES_CONTROL_MISC_DEFAULT     0x0000
#define mmnbif_gpuBIF_GFX_DRV_VPU_RST_DEFAULT           0x0000
#define mmnbif_gpuBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT  0x0008
#define mmnbif_gpuBIF_GFX_VF_FLR_PROTECT_DEFAULT        0x0000
#define mmnbif_gpuBIF_GMI_WRR_WEIGHT_DEFAULT            0x40404
#define mmnbif_gpuBIF_IH_DOORBELL_RANGE_DEFAULT         0x0000
#define mmnbif_gpuBIF_INST_RESET_INTR_MASK_DEFAULT      0x0000
#define mmnbif_gpuBIF_INST_RESET_INTR_STS_DEFAULT       0x0000
#define mmnbif_gpuBIF_IOHUB_RAS_IH_CNTL_DEFAULT         0x0000
#define mmnbif_gpuBIF_MMSCH0_DOORBELL_RANGE_DEFAULT     0x0000
#define mmnbif_gpuBIF_MM_INDACCESS_CNTL_DEFAULT         0x0000
#define mmnbif_gpuBIF_MST_TRANS_PENDING_VF_DEFAULT      0x0000
#define mmnbif_gpuBIF_PERSTB_PAD_CNTL_DEFAULT           0x00C0
#define mmnbif_gpuBIF_PF0_VF_FLR_INTR_MASK_DEFAULT      0x0000
#define mmnbif_gpuBIF_PF0_VF_FLR_INTR_STS_DEFAULT       0x0000
#define mmnbif_gpuBIF_PF0_VF_FLR_RST_DEFAULT            0x0000
#define mmnbif_gpuBIF_PF_DSTATE_INTR_MASK_DEFAULT       0x0000
#define mmnbif_gpuBIF_PF_DSTATE_INTR_STS_DEFAULT        0x0000
#define mmnbif_gpuBIF_PF_FLR_INTR_MASK_DEFAULT          0x0000
#define mmnbif_gpuBIF_PF_FLR_INTR_STS_DEFAULT           0x0000
#define mmnbif_gpuBIF_PF_FLR_PROTECT_DEFAULT            0x0000
#define mmnbif_gpuBIF_PF_FLR_RST_DEFAULT                0x0000
#define mmnbif_gpuBIF_PORT0_DSTATE_VALUE_DEFAULT        0x0000
#define mmnbif_gpuBIF_POWER_INTR_MASK_DEFAULT           0x0000
#define mmnbif_gpuBIF_POWER_INTR_STS_DEFAULT            0x0000
#define mmnbif_gpuBIF_PX_EN_PAD_CNTL_DEFAULT            0x0031
#define mmnbif_gpuBIF_RAS_MISC_CTRL_DEFAULT__GFX09      0x0000
#define mmnbif_gpuBIF_RAS_VWR_FROM_IOHUB_DEFAULT        0x0000
#define mmnbif_gpuBIF_RB_BASE_DEFAULT                   0x0000
#define mmnbif_gpuBIF_RB_CNTL_DEFAULT                   0x0000
#define mmnbif_gpuBIF_RB_RPTR_DEFAULT                   0x0000
#define mmnbif_gpuBIF_RB_WPTR_ADDR_HI_DEFAULT           0x0000
#define mmnbif_gpuBIF_RB_WPTR_ADDR_LO_DEFAULT           0x0000
#define mmnbif_gpuBIF_RB_WPTR_DEFAULT                   0x0000
#define mmnbif_gpuBIF_REFPADKIN_PAD_CNTL_DEFAULT        0x0007
#define mmnbif_gpuBIF_RLC_INTR_CNTL_DEFAULT             0x0000
#define mmnbif_gpuBIF_RST_GFXVF_FLR_IDLE_DEFAULT        0x0000
#define mmnbif_gpuBIF_RST_MISC_CTRL2_DEFAULT            0x0000
#define mmnbif_gpuBIF_RST_MISC_CTRL3_DEFAULT            0x104900
#define mmnbif_gpuBIF_RST_MISC_CTRL_DEFAULT             0xE0648
#define mmnbif_gpuBIF_SCRATCH0_DEFAULT                  0x0000
#define mmnbif_gpuBIF_SCRATCH1_DEFAULT                  0x0000
#define mmnbif_gpuBIF_SDMA0_DOORBELL_RANGE_DEFAULT      0x0000
#define mmnbif_gpuBIF_SDMA1_DOORBELL_RANGE_DEFAULT      0x0000
#define mmnbif_gpuBIF_SELFRING_BUFFER_VID_DEFAULT       0x605F
#define mmnbif_gpuBIF_SELFRING_VECTOR_CNTL_DEFAULT      0x0000
#define mmnbif_gpuBIF_SLV_TRANS_PENDING_VF_DEFAULT      0x0000
#define mmnbif_gpuBIF_TRANS_PENDING_DEFAULT             0x0000
#define mmnbif_gpuBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT       0x0008
#define mmnbif_gpuBIF_UVD_INTR_CNTL_DEFAULT             0x0000
#define mmnbif_gpuBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT       0x0008
#define mmnbif_gpuBIF_VCE_INTR_CNTL_DEFAULT             0x0000
#define mmnbif_gpuBIF_VDDGFX_FB_CMP_DEFAULT             0x0000
#define mmnbif_gpuBIF_VDDGFX_GFX0_LOWER_DEFAULT         0xC0008000
#define mmnbif_gpuBIF_VDDGFX_GFX0_UPPER_DEFAULT         0xCFFC
#define mmnbif_gpuBIF_VDDGFX_GFX1_LOWER_DEFAULT         0xC0028000
#define mmnbif_gpuBIF_VDDGFX_GFX1_UPPER_DEFAULT         0x31FFC
#define mmnbif_gpuBIF_VDDGFX_GFX2_LOWER_DEFAULT         0xC0034000
#define mmnbif_gpuBIF_VDDGFX_GFX2_UPPER_DEFAULT         0x37FFC
#define mmnbif_gpuBIF_VDDGFX_GFX3_LOWER_DEFAULT         0xC003C000
#define mmnbif_gpuBIF_VDDGFX_GFX3_UPPER_DEFAULT         0x3E1FC
#define mmnbif_gpuBIF_VDDGFX_GFX4_LOWER_DEFAULT         0xC003EC00
#define mmnbif_gpuBIF_VDDGFX_GFX4_UPPER_DEFAULT         0x3F1FC
#define mmnbif_gpuBIF_VDDGFX_GFX5_LOWER_DEFAULT         0xC003FC00
#define mmnbif_gpuBIF_VDDGFX_GFX5_UPPER_DEFAULT         0x3FFFC
#define mmnbif_gpuBIF_VDDGFX_RSV1_LOWER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV1_UPPER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV2_LOWER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV2_UPPER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV3_LOWER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV3_UPPER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV4_LOWER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VDDGFX_RSV4_UPPER_DEFAULT         0x0000
#define mmnbif_gpuBIF_VMHV_MAILBOX_DEFAULT              0x0000
#define mmnbif_gpuBIST_epf_DEFAULT__GFX09               0x0000
#define mmnbif_gpuBIST_epvf_DEFAULT                     0x0000
#define mmnbif_gpuBIST_swds_DEFAULT                     0x0000
#define mmnbif_gpuBME_DUMMY_CNTL_0_DEFAULT              0xAAAA
#define mmnbif_gpuBUS_CNTL_DEFAULT                      0x0000
#define mmnbif_gpuBX_RESET_CNTL_DEFAULT                 0x0000
#define mmnbif_gpuBX_RESET_EN_DEFAULT                   0x10003
#define mmnbif_gpuCACHE_LINE_epf_DEFAULT__GFX09         0x0000
#define mmnbif_gpuCACHE_LINE_epvf_DEFAULT               0x0000
#define mmnbif_gpuCACHE_LINE_swds_DEFAULT               0x0000
#define mmnbif_gpuCAP_PTR_epf_DEFAULT__GFX09            0x0000
#define mmnbif_gpuCAP_PTR_swds_DEFAULT                  0x0050
#define mmnbif_gpuCC_BIF_BX_PINSTRAP0_DEFAULT           0x0000
#define mmnbif_gpuCC_BIF_BX_STRAP0_DEFAULT              0x0000
#define mmnbif_gpuCLKREQB_PAD_CNTL_DEFAULT              0x08E0
#define mmnbif_gpuCOMMAND_epf_DEFAULT__GFX09            0x0000
#define mmnbif_gpuCOMMAND_epvf_DEFAULT                  0x0000
#define mmnbif_gpuCOMMAND_swds_DEFAULT                  0x0000
#define mmnbif_gpuDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF0_FLR_RST_CTRL_DEFAULT         0x8206A0A9
#define mmnbif_gpuDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF1_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF2_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF3_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF4_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF5_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF6_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT     0x001B
#define mmnbif_gpuDEV0_PF7_FLR_RST_CTRL_DEFAULT         0x2060009
#define mmnbif_gpuDEVICE_CAP2_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuDEVICE_CAP2_epvf_DEFAULT              0x0000
#define mmnbif_gpuDEVICE_CAP2_swds_DEFAULT              0x0000
#define mmnbif_gpuDEVICE_CAP_epf_DEFAULT__GFX09         0x10000020
#define mmnbif_gpuDEVICE_CAP_swds_DEFAULT               0x0020
#define mmnbif_gpuDEVICE_CNTL2_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuDEVICE_CNTL2_epvf_DEFAULT             0x0000
#define mmnbif_gpuDEVICE_CNTL2_swds_DEFAULT             0x0000
#define mmnbif_gpuDEVICE_CNTL_epf_DEFAULT__GFX09        0x2810
#define mmnbif_gpuDEVICE_CNTL_epvf_DEFAULT              0x0000
#define mmnbif_gpuDEVICE_CNTL_swds_DEFAULT              0x2810
#define mmnbif_gpuDEVICE_ID_epf_DEFAULT__GFX09          0x0000
#define mmnbif_gpuDEVICE_ID_epvf_DEFAULT                0xFFFF
#define mmnbif_gpuDEVICE_ID_swds_DEFAULT                0x0000
#define mmnbif_gpuDEVICE_STATUS2_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuDEVICE_STATUS2_epvf_DEFAULT           0x0000
#define mmnbif_gpuDEVICE_STATUS2_swds_DEFAULT           0x0000
#define mmnbif_gpuDEVICE_STATUS_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuDEVICE_STATUS_epvf_DEFAULT            0x0000
#define mmnbif_gpuDEVICE_STATUS_swds_DEFAULT            0x0000
#define mmnbif_gpuDN_PCIE_BUS_CNTL_DEFAULT              0x0080
#define mmnbif_gpuDN_PCIE_CFG_CNTL_DEFAULT              0x0000
#define mmnbif_gpuDN_PCIE_CNTL_DEFAULT                  0x0000
#define mmnbif_gpuDN_PCIE_CONFIG_CNTL_DEFAULT           0x0000
#define mmnbif_gpuDN_PCIE_HW_DEBUG_DEFAULT              0x0000
#define mmnbif_gpuDN_PCIE_RESERVED_DEFAULT              0xFFFFFFFF
#define mmnbif_gpuDN_PCIE_RX_CNTL2_DEFAULT              0x0000
#define mmnbif_gpuDN_PCIE_SCRATCH_DEFAULT               0x0000
#define mmnbif_gpuDN_PCIE_STRAP_F0_DEFAULT              0x0001
#define mmnbif_gpuDN_PCIE_STRAP_MISC2_DEFAULT           0x0000
#define mmnbif_gpuDN_PCIE_STRAP_MISC_DEFAULT            0x0000
#define mmnbif_gpuDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x0000
#define mmnbif_gpuDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x0000
#define mmnbif_gpuDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x0100
#define mmnbif_gpuEP_PCIEP_HW_DEBUG_DEFAULT             0x0000
#define mmnbif_gpuEP_PCIEP_RESERVED_DEFAULT             0xFFFFFFFF
#define mmnbif_gpuEP_PCIE_BUS_CNTL_DEFAULT              0x0080
#define mmnbif_gpuEP_PCIE_CFG_CNTL_DEFAULT              0x0000
#define mmnbif_gpuEP_PCIE_CNTL_DEFAULT                  0x0100
#define mmnbif_gpuEP_PCIE_ERR_CNTL_DEFAULT              0x0500
#define mmnbif_gpuEP_PCIE_F0_DPA_CAP_DEFAULT            0x190A1000
#define mmnbif_gpuEP_PCIE_F0_DPA_CNTL_DEFAULT           0x0100
#define mmnbif_gpuEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x00F0
#define mmnbif_gpuEP_PCIE_HW_DEBUG_DEFAULT              0x0000
#define mmnbif_gpuEP_PCIE_INT_CNTL_DEFAULT              0x0000
#define mmnbif_gpuEP_PCIE_INT_STATUS_DEFAULT            0x0000
#define mmnbif_gpuEP_PCIE_LC_SPEED_CNTL_DEFAULT         0x0000
#define mmnbif_gpuEP_PCIE_PME_CONTROL_DEFAULT           0x0000
#define mmnbif_gpuEP_PCIE_RX_CNTL2_DEFAULT              0x0000
#define mmnbif_gpuEP_PCIE_RX_CNTL_DEFAULT               0x1000000
#define mmnbif_gpuEP_PCIE_SCRATCH_DEFAULT               0x0000
#define mmnbif_gpuEP_PCIE_STRAP_MISC2_DEFAULT           0x0000
#define mmnbif_gpuEP_PCIE_STRAP_MISC_DEFAULT            0x0000
#define mmnbif_gpuEP_PCIE_TX_CNTL_DEFAULT               0x0000
#define mmnbif_gpuEP_PCIE_TX_LTR_CNTL_DEFAULT           0x7468
#define mmnbif_gpuEP_PCIE_TX_REQUESTER_ID_DEFAULT       0x0000
#define mmnbif_gpuGFXMSIX_PBA_DEFAULT                   0x0000
#define mmnbif_gpuGFXMSIX_VECT0_ADDR_HI_DEFAULT         0x0000
#define mmnbif_gpuGFXMSIX_VECT0_ADDR_LO_DEFAULT         0x0000
#define mmnbif_gpuGFXMSIX_VECT0_CONTROL_DEFAULT         0x0001
#define mmnbif_gpuGFXMSIX_VECT0_MSG_DATA_DEFAULT        0x0000
#define mmnbif_gpuGFXMSIX_VECT1_ADDR_HI_DEFAULT         0x0000
#define mmnbif_gpuGFXMSIX_VECT1_ADDR_LO_DEFAULT         0x0000
#define mmnbif_gpuGFXMSIX_VECT1_CONTROL_DEFAULT         0x0001
#define mmnbif_gpuGFXMSIX_VECT1_MSG_DATA_DEFAULT        0x0000
#define mmnbif_gpuGFXMSIX_VECT2_ADDR_HI_DEFAULT         0x0000
#define mmnbif_gpuGFXMSIX_VECT2_ADDR_LO_DEFAULT         0x0000
#define mmnbif_gpuGFXMSIX_VECT2_CONTROL_DEFAULT         0x0001
#define mmnbif_gpuGFXMSIX_VECT2_MSG_DATA_DEFAULT        0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR0_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR1_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR2_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR3_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR4_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR5_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR6_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ADDR7_DEFAULT         0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_CNTL_DEFAULT          0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ONE_CPL_DEFAULT       0xFFFFFFFF
#define mmnbif_gpuGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT   0x0000
#define mmnbif_gpuGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT      0x0000
#define mmnbif_gpuGPU_HDP_FLUSH_DONE_DEFAULT            0x0000
#define mmnbif_gpuGPU_HDP_FLUSH_REQ_DEFAULT             0x0000
#define mmnbif_gpuHARD_RST_CTRL_DEFAULT                 0xB0000055
#define mmnbif_gpuHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT  0x0000
#define mmnbif_gpuHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT  0x0000
#define mmnbif_gpuHEADER_epf_DEFAULT__GFX09             0x0000
#define mmnbif_gpuHEADER_epvf_DEFAULT                   0x0000
#define mmnbif_gpuHEADER_swds_DEFAULT                   0x0001
#define mmnbif_gpuHW_DEBUG_DEFAULT                      0x0000
#define mmnbif_gpuINTERRUPT_CNTL2_DEFAULT               0x0000
#define mmnbif_gpuINTERRUPT_CNTL_DEFAULT                0x0000
#define mmnbif_gpuINTERRUPT_LINE_epf_DEFAULT__GFX09     0x00FF
#define mmnbif_gpuINTERRUPT_LINE_epvf_DEFAULT           0x0000
#define mmnbif_gpuINTERRUPT_LINE_swds_DEFAULT           0x00FF
#define mmnbif_gpuINTERRUPT_PIN_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuINTERRUPT_PIN_epvf_DEFAULT            0x0000
#define mmnbif_gpuINTR_LINE_ENABLE_DEFAULT              0x0000
#define mmnbif_gpuINTR_LINE_POLARITY_DEFAULT            0x0000
#define mmnbif_gpuIO_BASE_LIMIT_HI_swds_DEFAULT         0x0000
#define mmnbif_gpuIO_BASE_LIMIT_swds_DEFAULT            0x0101
#define mmnbif_gpuIRQ_BRIDGE_CNTL_swds_DEFAULT          0x0000
#define mmnbif_gpuLATENCY_epf_DEFAULT__GFX09            0x0000
#define mmnbif_gpuLATENCY_epvf_DEFAULT                  0x0000
#define mmnbif_gpuLATENCY_swds_DEFAULT                  0x0000
#define mmnbif_gpuLINK_CAP2_epf_DEFAULT__GFX09          0x000E
#define mmnbif_gpuLINK_CAP2_epvf_DEFAULT                0x000E
#define mmnbif_gpuLINK_CAP2_swds_DEFAULT                0x000E
#define mmnbif_gpuLINK_CAP_epf_DEFAULT__GFX09           0x411C03
#define mmnbif_gpuLINK_CNTL2_epf_DEFAULT__GFX09         0x0003
#define mmnbif_gpuLINK_CNTL2_epvf_DEFAULT               0x0000
#define mmnbif_gpuLINK_CNTL2_swds_DEFAULT               0x0003
#define mmnbif_gpuLINK_CNTL_epf_DEFAULT__GFX09          0x0000
#define mmnbif_gpuLINK_CNTL_epvf_DEFAULT                0x0000
#define mmnbif_gpuLINK_CNTL_swds_DEFAULT                0x0000
#define mmnbif_gpuLINK_STATUS2_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuLINK_STATUS2_epvf_DEFAULT             0x0000
#define mmnbif_gpuLINK_STATUS2_swds_DEFAULT             0x0000
#define mmnbif_gpuLINK_STATUS_epf_DEFAULT__GFX09        0x1001
#define mmnbif_gpuLINK_STATUS_epvf_DEFAULT              0x0000
#define mmnbif_gpuLINK_STATUS_swds_DEFAULT              0x3001
#define mmnbif_gpuLTR_MSG_INFO_FROM_EP_DEFAULT          0x0000
#define mmnbif_gpuMAILBOX_CONTROL_DEFAULT               0x0000
#define mmnbif_gpuMAILBOX_INDEX_DEFAULT                 0x0000
#define mmnbif_gpuMAILBOX_INT_CNTL_DEFAULT              0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_RCV_DW0_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_RCV_DW1_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_RCV_DW2_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_RCV_DW3_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_TRN_DW0_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_TRN_DW1_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_TRN_DW2_DEFAULT        0x0000
#define mmnbif_gpuMAILBOX_MSGBUF_TRN_DW3_DEFAULT        0x0000
#define mmnbif_gpuMAX_LATENCY_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuMEM_BASE_LIMIT_swds_DEFAULT           0x0000
#define mmnbif_gpuMEM_TYPE_CNTL_DEFAULT                 0x0000
#define mmnbif_gpuMIN_GRANT_epf_DEFAULT__GFX09          0x0000
#define mmnbif_gpuMISC_SCRATCH_DEFAULT                  0x0000
#define mmnbif_gpuMISC_SECURITY_SET2_DEFAULT            0x015A
#define mmnbif_gpuMISC_SECURITY_SET_DEFAULT             0x0000
#define mmnbif_gpuMM_CFGREGS_CNTL_DEFAULT               0x0000
#define mmnbif_gpuMM_DATA_DEFAULT                       0x0000
#define mmnbif_gpuMM_INDEX_DEFAULT                      0x0000
#define mmnbif_gpuMM_INDEX_HI_DEFAULT                   0x0000
#define mmnbif_gpuMSIX_CAP_LIST_epf_DEFAULT__GFX09      0x0011
#define mmnbif_gpuMSIX_CAP_LIST_epvf_DEFAULT            0x0011
#define mmnbif_gpuMSIX_MSG_CNTL_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuMSIX_MSG_CNTL_epvf_DEFAULT            0x0000
#define mmnbif_gpuMSIX_PBA_epf_DEFAULT__GFX09           0x0000
#define mmnbif_gpuMSIX_PBA_epvf_DEFAULT                 0x0000
#define mmnbif_gpuMSIX_TABLE_epf_DEFAULT__GFX09         0x0000
#define mmnbif_gpuMSIX_TABLE_epvf_DEFAULT               0x0000
#define mmnbif_gpuMSI_CAP_LIST_epf_DEFAULT__GFX09       0xC005
#define mmnbif_gpuMSI_CAP_LIST_epvf_DEFAULT             0xC005
#define mmnbif_gpuMSI_CAP_LIST_swds_DEFAULT             0xC005
#define mmnbif_gpuMSI_MASK_64_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuMSI_MASK_64_epvf_DEFAULT              0x0000
#define mmnbif_gpuMSI_MASK_epf_DEFAULT__GFX09           0x0000
#define mmnbif_gpuMSI_MASK_epvf_DEFAULT                 0x0000
#define mmnbif_gpuMSI_MSG_ADDR_HI_epf_DEFAULT__GFX09    0x0000
#define mmnbif_gpuMSI_MSG_ADDR_HI_epvf_DEFAULT          0x0000
#define mmnbif_gpuMSI_MSG_ADDR_HI_swds_DEFAULT          0x0000
#define mmnbif_gpuMSI_MSG_ADDR_LO_epf_DEFAULT__GFX09    0x0000
#define mmnbif_gpuMSI_MSG_ADDR_LO_epvf_DEFAULT          0x0000
#define mmnbif_gpuMSI_MSG_ADDR_LO_swds_DEFAULT          0x0000
#define mmnbif_gpuMSI_MSG_CNTL_epf_DEFAULT__GFX09       0x0080
#define mmnbif_gpuMSI_MSG_CNTL_swds_DEFAULT             0x0080
#define mmnbif_gpuMSI_MSG_DATA_64_epf_DEFAULT__GFX09    0x0000
#define mmnbif_gpuMSI_MSG_DATA_64_epvf_DEFAULT          0x0000
#define mmnbif_gpuMSI_MSG_DATA_64_swds_DEFAULT          0x0000
#define mmnbif_gpuMSI_MSG_DATA_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuMSI_MSG_DATA_epvf_DEFAULT             0x0000
#define mmnbif_gpuMSI_MSG_DATA_swds_DEFAULT             0x0000
#define mmnbif_gpuMSI_PENDING_64_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuMSI_PENDING_64_epvf_DEFAULT           0x0000
#define mmnbif_gpuMSI_PENDING_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuMSI_PENDING_epvf_DEFAULT              0x0000
#define mmnbif_gpuNBIF_DS_CTRL_LCLK_DEFAULT             0x1000000
#define mmnbif_gpuNBIF_MGCG_CTRL_LCLK_DEFAULT           0x0080
#define mmnbif_gpuNBIF_REGIF_ERRSET_CTRL_DEFAULT        0x0000
#define mmnbif_gpuNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT    0x0000
#define mmnbif_gpuNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT   0x0000
#define mmnbif_gpuNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT   0x0000
#define mmnbif_gpuNBIF_SDP_VWR_VCHG_TRIG_DEFAULT        0x0000
#define mmnbif_gpuNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT  0x0000
#define mmnbif_gpuNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT    0x0000
#define mmnbif_gpuNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT   0x0000
#define mmnbif_gpuNBIF_SMN_VWR_VCHG_TRIG_DEFAULT        0x0000
#define mmnbif_gpuNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT       0x0000
#define mmnbif_gpuNBIF_STRAP_WRITE_CTRL_DEFAULT         0x0000
#define mmnbif_gpuNBIF_VWIRE_CTRL_DEFAULT               0x0000
#define mmnbif_gpuNGDC_RESERVED_0_DEFAULT               0x0000
#define mmnbif_gpuNGDC_RESERVED_1_DEFAULT               0x0000
#define mmnbif_gpuNGDC_SDP_PORT_CTRL_DEFAULT            0x000F
#define mmnbif_gpuNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT     0x000F
#define mmnbif_gpuOUTSTANDING_VC_ALLOC_DEFAULT          0x6F06C0CF
#define mmnbif_gpuPCIEMSIX_PBA_DEFAULT__GFX09           0x0000
#define mmnbif_gpuPCIEMSIX_VECT0_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT0_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT0_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT0_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT10_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT10_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT10_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT10_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT11_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT11_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT11_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT11_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT12_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT12_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT12_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT12_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT13_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT13_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT13_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT13_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT14_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT14_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT14_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT14_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT15_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT15_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT15_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT15_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT16_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT16_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT16_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT16_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT17_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT17_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT17_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT17_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT18_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT18_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT18_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT18_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT19_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT19_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT19_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT19_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT1_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT1_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT1_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT1_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT20_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT20_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT20_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT20_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT21_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT21_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT21_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT21_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT22_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT22_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT22_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT22_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT23_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT23_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT23_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT23_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT24_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT24_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT24_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT24_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT25_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT25_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT25_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT25_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT26_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT26_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT26_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT26_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT27_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT27_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT27_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT27_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT28_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT28_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT28_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT28_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT29_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT29_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT29_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT29_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT2_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT2_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT2_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT2_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT30_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT30_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT30_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT30_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT31_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT31_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT31_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT31_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT3_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT3_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT3_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT3_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT4_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT4_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT4_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT4_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT5_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT5_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT5_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT5_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT6_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT6_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT6_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT6_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT7_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT7_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT7_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT7_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT8_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT8_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT8_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT8_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT9_ADDR_HI_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT9_ADDR_LO_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT9_CONTROL_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEMSIX_VECT9_MSG_DATA_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIEP_HW_DEBUG_DEFAULT                0x0000
#define mmnbif_gpuPCIEP_STRAP_MISC_DEFAULT              0x0000
#define mmnbif_gpuPCIE_ACS_CAP_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_ACS_CAP_swds_DEFAULT             0x0000
#define mmnbif_gpuPCIE_ACS_CNTL_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_ACS_CNTL_swds_DEFAULT            0x0000
#define mmnbif_gpuPCIE_ACS_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2B01000D
#define mmnbif_gpuPCIE_ACS_ENH_CAP_LIST_swds_DEFAULT    0x2F01000D
#define mmnbif_gpuPCIE_ADV_ERR_CAP_CNTL_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_ADV_ERR_CAP_CNTL_epvf_DEFAULT    0x0000
#define mmnbif_gpuPCIE_ADV_ERR_CAP_CNTL_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x20020001
#define mmnbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_DEFAULT 0x20020001
#define mmnbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds_DEFAULT 0x20020001
#define mmnbif_gpuPCIE_ARI_CAP_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_ARI_CAP_epvf_DEFAULT             0x0000
#define mmnbif_gpuPCIE_ARI_CNTL_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_ARI_CNTL_epvf_DEFAULT            0x0000
#define mmnbif_gpuPCIE_ARI_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x3301000E
#define mmnbif_gpuPCIE_ARI_ENH_CAP_LIST_epvf_DEFAULT    0x3301000E
#define mmnbif_gpuPCIE_ATS_CAP_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_ATS_CAP_epvf_DEFAULT             0x0000
#define mmnbif_gpuPCIE_ATS_CNTL_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_ATS_CNTL_epvf_DEFAULT            0x0000
#define mmnbif_gpuPCIE_ATS_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2C01000F
#define mmnbif_gpuPCIE_ATS_ENH_CAP_LIST_epvf_DEFAULT    0x2C01000F
#define mmnbif_gpuPCIE_BAR1_CAP_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_BAR1_CNTL_epf_DEFAULT__GFX09     0x0020
#define mmnbif_gpuPCIE_BAR2_CAP_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_BAR2_CNTL_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPCIE_BAR3_CAP_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_BAR3_CNTL_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPCIE_BAR4_CAP_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_BAR4_CNTL_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPCIE_BAR5_CAP_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_BAR5_CNTL_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPCIE_BAR6_CAP_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_BAR6_CNTL_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPCIE_BAR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x24010015
#define mmnbif_gpuPCIE_CAP_LIST_epf_DEFAULT__GFX09      0xA010
#define mmnbif_gpuPCIE_CAP_LIST_epvf_DEFAULT            0xA010
#define mmnbif_gpuPCIE_CAP_LIST_swds_DEFAULT            0xA010
#define mmnbif_gpuPCIE_CAP_epf_DEFAULT__GFX09           0x0002
#define mmnbif_gpuPCIE_CAP_epvf_DEFAULT                 0x0002
#define mmnbif_gpuPCIE_CAP_swds_DEFAULT                 0x0062
#define mmnbif_gpuPCIE_CORR_ERR_MASK_epf_DEFAULT__GFX09 0x2000
#define mmnbif_gpuPCIE_CORR_ERR_MASK_epvf_DEFAULT       0x0000
#define mmnbif_gpuPCIE_CORR_ERR_MASK_swds_DEFAULT       0x2000
#define mmnbif_gpuPCIE_CORR_ERR_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_CORR_ERR_STATUS_epvf_DEFAULT     0x0000
#define mmnbif_gpuPCIE_CORR_ERR_STATUS_swds_DEFAULT     0x0000
#define mmnbif_gpuPCIE_DATA2_DEFAULT                    0x0000
#define mmnbif_gpuPCIE_DATA_DEFAULT                     0x0000
#define mmnbif_gpuPCIE_DEV_SERIAL_NUM_DW1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DEV_SERIAL_NUM_DW1_swds_DEFAULT  0x0000
#define mmnbif_gpuPCIE_DEV_SERIAL_NUM_DW2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DEV_SERIAL_NUM_DW2_swds_DEFAULT  0x0000
#define mmnbif_gpuPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x15010003
#define mmnbif_gpuPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds_DEFAULT 0x15010003
#define mmnbif_gpuPCIE_DPA_CAP_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_DPA_CNTL_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_DPA_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x27010016
#define mmnbif_gpuPCIE_DPA_LATENCY_INDICATOR_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_STATUS_epf_DEFAULT__GFX09    0x0100
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_ERR_CNTL_DEFAULT                 0x0500
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00FA
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00C8
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x0096
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x0064
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x004B
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x0032
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x0019
#define mmnbif_gpuPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x000A
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00FA
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00C8
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x0096
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x0064
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x004B
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x0032
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x0019
#define mmnbif_gpuPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x000A
#define mmnbif_gpuPCIE_HDR_LOG0_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_HDR_LOG0_epvf_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG0_swds_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG1_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_HDR_LOG1_epvf_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG1_swds_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG2_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_HDR_LOG2_epvf_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG2_swds_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG3_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_HDR_LOG3_epvf_DEFAULT            0x0000
#define mmnbif_gpuPCIE_HDR_LOG3_swds_DEFAULT            0x0000
#define mmnbif_gpuPCIE_INDEX2_DEFAULT                   0x0000
#define mmnbif_gpuPCIE_INDEX_DEFAULT                    0x0000
#define mmnbif_gpuPCIE_LANE_0_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_0_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_10_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_10_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_11_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_11_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_12_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_12_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_13_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_13_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_14_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_14_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_15_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_15_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_1_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_1_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_2_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_2_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_3_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_3_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_4_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_4_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_5_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_5_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_6_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_6_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_7_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_7_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_8_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_8_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_9_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define mmnbif_gpuPCIE_LANE_9_EQUALIZATION_CNTL_swds_DEFAULT 0x7F0F
#define mmnbif_gpuPCIE_LANE_ERROR_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_LANE_ERROR_STATUS_swds_DEFAULT   0x0000
#define mmnbif_gpuPCIE_LC_CNTL2_DEFAULT                 0x0000
#define mmnbif_gpuPCIE_LC_SPEED_CNTL_DEFAULT            0x0000
#define mmnbif_gpuPCIE_LINK_CNTL3_epf_DEFAULT__GFX09    0x0000
#define mmnbif_gpuPCIE_LINK_CNTL3_swds_DEFAULT          0x0000
#define mmnbif_gpuPCIE_LTR_CAP_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_LTR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x32810018
#define mmnbif_gpuPCIE_MC_ADDR0_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_MC_ADDR1_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuPCIE_MC_BLOCK_ALL0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_MC_BLOCK_ALL1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_MC_BLOCK_UNTRANSLATED_0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_MC_BLOCK_UNTRANSLATED_1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_MC_CAP_epf_DEFAULT__GFX09        0x003F
#define mmnbif_gpuPCIE_MC_CNTL_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_MC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x32010012
#define mmnbif_gpuPCIE_MC_RCV0_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_MC_RCV1_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuPCIE_OUTSTAND_PAGE_REQ_ALLOC_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PAGE_REQ_CNTL_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PAGE_REQ_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2D010013
#define mmnbif_gpuPCIE_PAGE_REQ_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PASID_CAP_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPCIE_PASID_CNTL_epf_DEFAULT__GFX09    0x0000
#define mmnbif_gpuPCIE_PASID_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2E01001B
#define mmnbif_gpuPCIE_PORT_VC_CAP_REG1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PORT_VC_CAP_REG1_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_PORT_VC_CAP_REG2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PORT_VC_CAP_REG2_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_PORT_VC_CNTL_epf_DEFAULT__GFX09  0x0000
#define mmnbif_gpuPCIE_PORT_VC_CNTL_swds_DEFAULT        0x0000
#define mmnbif_gpuPCIE_PORT_VC_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PORT_VC_STATUS_swds_DEFAULT      0x0000
#define mmnbif_gpuPCIE_PWR_BUDGET_CAP_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PWR_BUDGET_DATA_SELECT_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PWR_BUDGET_DATA_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_PWR_BUDGET_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x25010004
#define mmnbif_gpuPCIE_RX_CNTL_DEFAULT                  0x0000
#define mmnbif_gpuPCIE_SECONDARY_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2A010019
#define mmnbif_gpuPCIE_SECONDARY_ENH_CAP_LIST_swds_DEFAULT 0x2A010019
#define mmnbif_gpuPCIE_SRIOV_CAP_epf_DEFAULT__GFX09     0x0002
#define mmnbif_gpuPCIE_SRIOV_CONTROL_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x40010010
#define mmnbif_gpuPCIE_SRIOV_FIRST_VF_OFFSET_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_FUNC_DEP_LINK_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_INITIAL_VFS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_NUM_VFS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_STATUS_epf_DEFAULT__GFX09  0x0000
#define mmnbif_gpuPCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_SYSTEM_PAGE_SIZE_epf_DEFAULT__GFX09 0x0001
#define mmnbif_gpuPCIE_SRIOV_TOTAL_VFS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_3_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_4_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_BASE_ADDR_5_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_DEVICE_ID_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_SRIOV_VF_STRIDE_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG0_epvf_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG0_swds_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG1_epvf_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG1_swds_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG2_epvf_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG2_swds_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG3_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG3_epvf_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TLP_PREFIX_LOG3_swds_DEFAULT     0x0000
#define mmnbif_gpuPCIE_TPH_REQR_CAP_epf_DEFAULT__GFX09  0x0000
#define mmnbif_gpuPCIE_TPH_REQR_CNTL_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_TPH_REQR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2F010017
#define mmnbif_gpuPCIE_UNCORR_ERR_MASK_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_UNCORR_ERR_MASK_epvf_DEFAULT     0x0000
#define mmnbif_gpuPCIE_UNCORR_ERR_MASK_swds_DEFAULT     0x0000
#define mmnbif_gpuPCIE_UNCORR_ERR_SEVERITY_epf_DEFAULT__GFX09 0x462030
#define mmnbif_gpuPCIE_UNCORR_ERR_SEVERITY_epvf_DEFAULT 0x0000
#define mmnbif_gpuPCIE_UNCORR_ERR_SEVERITY_swds_DEFAULT 0x462030
#define mmnbif_gpuPCIE_UNCORR_ERR_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_UNCORR_ERR_STATUS_epvf_DEFAULT   0x0000
#define mmnbif_gpuPCIE_UNCORR_ERR_STATUS_swds_DEFAULT   0x0000
#define mmnbif_gpuPCIE_VC0_RESOURCE_CAP_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VC0_RESOURCE_CAP_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_VC0_RESOURCE_CNTL_epf_DEFAULT__GFX09 0x800000FF
#define mmnbif_gpuPCIE_VC0_RESOURCE_CNTL_swds_DEFAULT   0x800000FF
#define mmnbif_gpuPCIE_VC0_RESOURCE_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VC0_RESOURCE_STATUS_swds_DEFAULT 0x0000
#define mmnbif_gpuPCIE_VC1_RESOURCE_CAP_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VC1_RESOURCE_CAP_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_VC1_RESOURCE_CNTL_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VC1_RESOURCE_CNTL_swds_DEFAULT   0x0000
#define mmnbif_gpuPCIE_VC1_RESOURCE_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VC1_RESOURCE_STATUS_swds_DEFAULT 0x0000
#define mmnbif_gpuPCIE_VC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x14010002
#define mmnbif_gpuPCIE_VC_ENH_CAP_LIST_swds_DEFAULT     0x14010002
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC1_epvf_DEFAULT    0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC1_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC2_epvf_DEFAULT    0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC2_swds_DEFAULT    0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf_DEFAULT__GFX09 0x1000B
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x1101000B
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_DEFAULT 0x1101000B
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds_DEFAULT 0x1101000B
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf_DEFAULT__GFX09 0x0000
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf_DEFAULT__GFX09 0xF020002
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_epf_DEFAULT__GFX09 0x1010001
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_epvf_DEFAULT 0x1010001
#define mmnbif_gpuPCIE_VENDOR_SPECIFIC_HDR_swds_DEFAULT 0x1010001
#define mmnbif_gpuPMI_CAP_LIST_epf_DEFAULT__GFX09       0x0001
#define mmnbif_gpuPMI_CAP_LIST_swds_DEFAULT             0x5801
#define mmnbif_gpuPMI_CAP_epf_DEFAULT__GFX09            0x0003
#define mmnbif_gpuPMI_STATUS_CNTL_epf_DEFAULT__GFX09    0x0000
#define mmnbif_gpuPMI_STATUS_CNTL_swds_DEFAULT          0x0000
#define mmnbif_gpuPREF_BASE_LIMIT_swds_DEFAULT          0x10001
#define mmnbif_gpuPREF_BASE_UPPER_swds_DEFAULT          0x0000
#define mmnbif_gpuPREF_LIMIT_UPPER_swds_DEFAULT         0x0000
#define mmnbif_gpuPROG_INTERFACE_epf_DEFAULT__GFX09     0x0000
#define mmnbif_gpuPROG_INTERFACE_epvf_DEFAULT           0x0000
#define mmnbif_gpuPROG_INTERFACE_swds_DEFAULT           0x0000
#define mmnbif_gpuRCC_BACO_CNTL_MISC_DEFAULT            0x0000
#define mmnbif_gpuRCC_BIF_STRAP0_DEFAULT                0x0000
#define mmnbif_gpuRCC_BIF_STRAP1_DEFAULT                0x0000
#define mmnbif_gpuRCC_BIF_STRAP2_DEFAULT                0x0000
#define mmnbif_gpuRCC_BIF_STRAP3_DEFAULT                0x0000
#define mmnbif_gpuRCC_BIF_STRAP4_DEFAULT                0x0000
#define mmnbif_gpuRCC_BIF_STRAP5_DEFAULT                0x1100000
#define mmnbif_gpuRCC_BIF_STRAP6_DEFAULT                0x0000
#define mmnbif_gpuRCC_BUSNUM_CNTL1_DEFAULT              0x0000
#define mmnbif_gpuRCC_BUSNUM_CNTL2_DEFAULT              0x0000
#define mmnbif_gpuRCC_BUSNUM_LIST0_DEFAULT              0x0000
#define mmnbif_gpuRCC_BUSNUM_LIST1_DEFAULT              0x0000
#define mmnbif_gpuRCC_BUS_CNTL_DEFAULT                  0x0000
#define mmnbif_gpuRCC_CAPTURE_HOST_BUSNUM_DEFAULT       0x0000
#define mmnbif_gpuRCC_CMN_LINK_CNTL_DEFAULT             0x400000
#define mmnbif_gpuRCC_CONFIG_APER_SIZE_DEFAULT          0x0000
#define mmnbif_gpuRCC_CONFIG_CNTL_DEFAULT               0x0000
#define mmnbif_gpuRCC_CONFIG_F0_BASE_DEFAULT            0x0000
#define mmnbif_gpuRCC_CONFIG_MEMSIZE_DEFAULT            0x0000
#define mmnbif_gpuRCC_CONFIG_REG_APER_SIZE_DEFAULT      0x0000
#define mmnbif_gpuRCC_CONFIG_RESERVED_DEFAULT           0x0000
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP1_DEFAULT          0x5530000
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP2_DEFAULT          0x2000000
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP3_DEFAULT          0x8B5A181
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP4_DEFAULT          0x1F000042
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP5_DEFAULT          0x1002
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP9_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP0_DEFAULT          0x30000000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP10_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP11_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP12_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP3_DEFAULT          0x806ABE1
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP4_DEFAULT          0x2F000000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP5_DEFAULT          0x1002
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF1_STRAP7_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF3_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF4_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF5_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF6_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_EPF7_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_LINK_CNTL_DEFAULT            0x0000
#define mmnbif_gpuRCC_DEV0_PORT_STRAP0_DEFAULT          0x54228E20
#define mmnbif_gpuRCC_DEV0_PORT_STRAP1_DEFAULT          0x10221471
#define mmnbif_gpuRCC_DEV0_PORT_STRAP2_DEFAULT          0x1C65E009
#define mmnbif_gpuRCC_DEV0_PORT_STRAP3_DEFAULT          0x5FFFF849
#define mmnbif_gpuRCC_DEV0_PORT_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV0_PORT_STRAP5_DEFAULT          0xAF800000
#define mmnbif_gpuRCC_DEV0_PORT_STRAP6_DEFAULT          0x0002
#define mmnbif_gpuRCC_DEV0_PORT_STRAP7_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF0_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF1_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP13_DEFAULT         0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_EPF2_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP1_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP2_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP3_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP4_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP5_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP6_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEV1_PORT_STRAP7_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEVFUNCNUM_LIST0_DEFAULT          0x0000
#define mmnbif_gpuRCC_DEVFUNCNUM_LIST1_DEFAULT          0x0000
#define mmnbif_gpuRCC_DOORBELL_APER_EN_DEFAULT          0x0000
#define mmnbif_gpuRCC_EP_REQUESTERID_RESTORE_DEFAULT    0x0000
#define mmnbif_gpuRCC_ERR_INT_CNTL_DEFAULT              0x0000
#define mmnbif_gpuRCC_ERR_LOG_DEFAULT                   0x0000
#define mmnbif_gpuRCC_FEATURES_CONTROL_MISC_DEFAULT     0x0000
#define mmnbif_gpuRCC_HOST_BUSNUM_DEFAULT               0x0000
#define mmnbif_gpuRCC_IOV_FUNC_IDENTIFIER_DEFAULT       0x0000
#define mmnbif_gpuRCC_LTR_LSWITCH_CNTL_DEFAULT          0x0000
#define mmnbif_gpuRCC_MH_ARB_CNTL_DEFAULT               0x0000
#define mmnbif_gpuRCC_PEER0_FB_OFFSET_HI_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER0_FB_OFFSET_LO_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER1_FB_OFFSET_HI_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER1_FB_OFFSET_LO_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER2_FB_OFFSET_HI_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER2_FB_OFFSET_LO_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER3_FB_OFFSET_HI_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER3_FB_OFFSET_LO_DEFAULT        0x0000
#define mmnbif_gpuRCC_PEER_REG_RANGE0_DEFAULT           0xFFFF0000
#define mmnbif_gpuRCC_PEER_REG_RANGE1_DEFAULT           0xFFFF0000
#define mmnbif_gpuRCC_PFC_AUXPWR_CNTL_DEFAULT           0x0000
#define mmnbif_gpuRCC_PFC_LTR_CNTL_DEFAULT              0x0000
#define mmnbif_gpuRCC_PFC_PME_RESTORE_DEFAULT           0x0000
#define mmnbif_gpuRCC_PFC_STICKY_RESTORE_0_DEFAULT      0x0000
#define mmnbif_gpuRCC_PFC_STICKY_RESTORE_1_DEFAULT      0x0000
#define mmnbif_gpuRCC_PFC_STICKY_RESTORE_2_DEFAULT      0x0000
#define mmnbif_gpuRCC_PFC_STICKY_RESTORE_3_DEFAULT      0x0000
#define mmnbif_gpuRCC_PFC_STICKY_RESTORE_4_DEFAULT      0x0000
#define mmnbif_gpuRCC_PFC_STICKY_RESTORE_5_DEFAULT      0x0000
#define mmnbif_gpuRCC_RESET_EN_DEFAULT                  0x8000
#define mmnbif_gpuRCC_VDM_SUPPORT_DEFAULT               0x0000
#define mmnbif_gpuRCC_XDMA_HI_DEFAULT                   0x0000
#define mmnbif_gpuRCC_XDMA_LO_DEFAULT                   0x0000
#define mmnbif_gpuREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT      0x385C
#define mmnbif_gpuREMAP_HDP_REG_FLUSH_CNTL_DEFAULT      0x3858
#define mmnbif_gpuREVISION_ID_epf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuREVISION_ID_epvf_DEFAULT              0x0000
#define mmnbif_gpuREVISION_ID_swds_DEFAULT              0x0000
#define mmnbif_gpuROM_BASE_ADDR_epf_DEFAULT__GFX09      0x0000
#define mmnbif_gpuROM_BASE_ADDR_epvf_DEFAULT            0x0000
#define mmnbif_gpuRSMU_SOFT_RST_CTRL_DEFAULT            0x90000000
#define mmnbif_gpuS2A_MISC_CNTL_DEFAULT                 0x0000
#define mmnbif_gpuSBIOS_SCRATCH_0_DEFAULT               0x0000
#define mmnbif_gpuSBIOS_SCRATCH_1_DEFAULT               0x0000
#define mmnbif_gpuSBIOS_SCRATCH_2_DEFAULT               0x0000
#define mmnbif_gpuSBIOS_SCRATCH_3_DEFAULT               0x0000
#define mmnbif_gpuSECONDARY_STATUS_swds_DEFAULT         0x0000
#define mmnbif_gpuSELF_SOFT_RST_DEFAULT                 0x0000
#define mmnbif_gpuSHADOW_BASE_ADDR_1_DEFAULT            0x0000
#define mmnbif_gpuSHADOW_BASE_ADDR_2_DEFAULT            0x0000
#define mmnbif_gpuSHADOW_COMMAND_DEFAULT                0x0000
#define mmnbif_gpuSHADOW_IO_BASE_LIMIT_DEFAULT          0x0000
#define mmnbif_gpuSHADOW_IO_BASE_LIMIT_HI_DEFAULT       0x0000
#define mmnbif_gpuSHADOW_IRQ_BRIDGE_CNTL_DEFAULT        0x0000
#define mmnbif_gpuSHADOW_MEM_BASE_LIMIT_DEFAULT         0x0000
#define mmnbif_gpuSHADOW_PREF_BASE_LIMIT_DEFAULT        0x10001
#define mmnbif_gpuSHADOW_PREF_BASE_UPPER_DEFAULT        0x0000
#define mmnbif_gpuSHADOW_PREF_LIMIT_UPPER_DEFAULT       0x0000
#define mmnbif_gpuSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x0000
#define mmnbif_gpuSHUB_GFX_DRV_VPU_RST_DEFAULT          0x0000
#define mmnbif_gpuSHUB_LINK_RESET_DEFAULT               0x0000
#define mmnbif_gpuSHUB_PF0_VF_FLR_RST_DEFAULT           0x0000
#define mmnbif_gpuSHUB_PF_FLR_RST_DEFAULT               0x0000
#define mmnbif_gpuSHUB_REGS_IF_CTL_DEFAULT              0x0000
#define mmnbif_gpuSHUB_RST_MISC_TRL_DEFAULT             0x100001
#define mmnbif_gpuSHUB_SDP_PORT_RST_DEFAULT             0x0000
#define mmnbif_gpuSHUB_SOFT_RST_CTRL_DEFAULT            0x0009
#define mmnbif_gpuSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_Req_TimeSlot_REG0_DEFAULT    0x0000
#define mmnbif_gpuSION_CL0_Req_TimeSlot_REG1_DEFAULT    0x0000
#define mmnbif_gpuSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_Req_TimeSlot_REG0_DEFAULT    0x0000
#define mmnbif_gpuSION_CL1_Req_TimeSlot_REG1_DEFAULT    0x0000
#define mmnbif_gpuSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_Req_TimeSlot_REG0_DEFAULT    0x0000
#define mmnbif_gpuSION_CL2_Req_TimeSlot_REG1_DEFAULT    0x0000
#define mmnbif_gpuSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_Req_TimeSlot_REG0_DEFAULT    0x0000
#define mmnbif_gpuSION_CL3_Req_TimeSlot_REG1_DEFAULT    0x0000
#define mmnbif_gpuSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x0000
#define mmnbif_gpuSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT  0x0000
#define mmnbif_gpuSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT  0x0000
#define mmnbif_gpuSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_Req_BurstTarget_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_Req_BurstTarget_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_Req_TimeSlot_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_Req_TimeSlot_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_Req_BurstTarget_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_Req_BurstTarget_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_Req_TimeSlot_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_Req_TimeSlot_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT__GFX09 0x0000
#define mmnbif_gpuSION_CNTL_REG0_DEFAULT                0x0000
#define mmnbif_gpuSION_CNTL_REG1_DEFAULT                0x0000
#define mmnbif_gpuSLOT_CAP2_epf_DEFAULT__GFX09          0x0000
#define mmnbif_gpuSLOT_CAP2_epvf_DEFAULT                0x0000
#define mmnbif_gpuSLOT_CAP2_swds_DEFAULT                0x0000
#define mmnbif_gpuSLOT_CAP_swds_DEFAULT                 0x0000
#define mmnbif_gpuSLOT_CNTL2_epf_DEFAULT__GFX09         0x0000
#define mmnbif_gpuSLOT_CNTL2_epvf_DEFAULT               0x0000
#define mmnbif_gpuSLOT_CNTL2_swds_DEFAULT               0x0000
#define mmnbif_gpuSLOT_CNTL_swds_DEFAULT                0x0000
#define mmnbif_gpuSLOT_STATUS2_epf_DEFAULT__GFX09       0x0000
#define mmnbif_gpuSLOT_STATUS2_epvf_DEFAULT             0x0000
#define mmnbif_gpuSLOT_STATUS2_swds_DEFAULT             0x0000
#define mmnbif_gpuSLOT_STATUS_swds_DEFAULT              0x0040
#define mmnbif_gpuSMN_MST_CNTL0_DEFAULT                 0x0001
#define mmnbif_gpuSMN_MST_CNTL1_DEFAULT                 0x0000
#define mmnbif_gpuSMN_MST_EP_CNTL1_DEFAULT              0x0000
#define mmnbif_gpuSMN_MST_EP_CNTL2_DEFAULT              0x0000
#define mmnbif_gpuSMN_MST_EP_CNTL3_DEFAULT              0x0000
#define mmnbif_gpuSMN_MST_EP_CNTL4_DEFAULT              0x0000
#define mmnbif_gpuSMN_MST_EP_CNTL5_DEFAULT              0x0000
#define mmnbif_gpuSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT     0x0000
#define mmnbif_gpuSSID_CAP_LIST_swds_DEFAULT            0x000D
#define mmnbif_gpuSSID_CAP_swds_DEFAULT                 0x0000
#define mmnbif_gpuSTATUS_epf_DEFAULT__GFX09             0x0010
#define mmnbif_gpuSTATUS_epvf_DEFAULT                   0x0010
#define mmnbif_gpuSTATUS_swds_DEFAULT                   0x0010
#define mmnbif_gpuSUB_BUS_NUMBER_LATENCY_swds_DEFAULT   0x0000
#define mmnbif_gpuSUB_CLASS_epf_DEFAULT__GFX09          0x0000
#define mmnbif_gpuSUB_CLASS_epvf_DEFAULT                0x0000
#define mmnbif_gpuSUC_DATA_DEFAULT                      0x0000
#define mmnbif_gpuSUC_INDEX_DEFAULT                     0x0000
#define mmnbif_gpuSUM_DATA_DEFAULT                      0x0000
#define mmnbif_gpuSUM_INDEX_DEFAULT                     0x0000
#define mmnbif_gpuSYSHUB_DATA_OVLP_DEFAULT              0x0000
#define mmnbif_gpuSYSHUB_INDEX_OVLP_DEFAULT             0x0000
#define mmnbif_gpuVENDOR_CAP_LIST_epf_DEFAULT__GFX09    0x85009
#define mmnbif_gpuVENDOR_ID_epf_DEFAULT__GFX09          0x0000
#define mmnbif_gpuVENDOR_ID_epvf_DEFAULT                0xFFFF
#define mmport_a_addr_DEFAULT                           0x0000
#define mmport_a_data_hi_DEFAULT                        0x0000
#define mmport_a_data_lo_DEFAULT                        0x0000
#define mmport_b_addr_DEFAULT                           0x0000
#define mmport_b_data_hi_DEFAULT                        0x0000
#define mmport_b_data_lo_DEFAULT                        0x0000
#define mmport_c_addr_DEFAULT                           0x0000
#define mmport_c_data_hi_DEFAULT                        0x0000
#define mmport_c_data_lo_DEFAULT                        0x0000
#define mmport_d_addr_DEFAULT                           0x0000
#define mmport_d_data_hi_DEFAULT                        0x0000
#define mmport_d_data_lo_DEFAULT                        0x0000
#define pcinbif_gpuADAPTER_ID_W_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuADAPTER_ID_epf_DEFAULT__GFX09        0x0000
#define pcinbif_gpuBASE_ADDR_1_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBASE_ADDR_1_epvf_DEFAULT             0x0000
#define pcinbif_gpuBASE_ADDR_1_swds_DEFAULT__GFX09      0x0000
#define pcinbif_gpuBASE_ADDR_2_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBASE_ADDR_2_epvf_DEFAULT             0x0000
#define pcinbif_gpuBASE_ADDR_3_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBASE_ADDR_3_epvf_DEFAULT             0x0000
#define pcinbif_gpuBASE_ADDR_4_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBASE_ADDR_4_epvf_DEFAULT             0x0000
#define pcinbif_gpuBASE_ADDR_5_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBASE_ADDR_5_epvf_DEFAULT             0x0000
#define pcinbif_gpuBASE_ADDR_6_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBASE_ADDR_6_epvf_DEFAULT             0x0000
#define pcinbif_gpuBASE_CLASS_epf_DEFAULT__GFX09        0x0000
#define pcinbif_gpuBASE_CLASS_epvf_DEFAULT              0x0000
#define pcinbif_gpuBASE_CLASS_swds_DEFAULT__GFX09       0x0000
#define pcinbif_gpuBIST_epf_DEFAULT__GFX09              0x0000
#define pcinbif_gpuBIST_epvf_DEFAULT                    0x0000
#define pcinbif_gpuBIST_swds_DEFAULT__GFX09             0x0000
#define pcinbif_gpuCACHE_LINE_epf_DEFAULT__GFX09        0x0000
#define pcinbif_gpuCACHE_LINE_epvf_DEFAULT              0x0000
#define pcinbif_gpuCACHE_LINE_swds_DEFAULT__GFX09       0x0000
#define pcinbif_gpuCAP_PTR_epf_DEFAULT__GFX09           0x0000
#define pcinbif_gpuCAP_PTR_swds_DEFAULT__GFX09          0x0050
#define pcinbif_gpuCOMMAND_epf_DEFAULT__GFX09           0x0000
#define pcinbif_gpuCOMMAND_epvf_DEFAULT                 0x0000
#define pcinbif_gpuCOMMAND_swds_DEFAULT__GFX09          0x0000
#define pcinbif_gpuDEVICE_CAP2_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuDEVICE_CAP2_epvf_DEFAULT             0x0000
#define pcinbif_gpuDEVICE_CAP2_swds_DEFAULT__GFX09      0x0000
#define pcinbif_gpuDEVICE_CAP_epf_DEFAULT__GFX09        0x10000020
#define pcinbif_gpuDEVICE_CAP_swds_DEFAULT__GFX09       0x0020
#define pcinbif_gpuDEVICE_CNTL2_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuDEVICE_CNTL2_epvf_DEFAULT            0x0000
#define pcinbif_gpuDEVICE_CNTL2_swds_DEFAULT__GFX09     0x0000
#define pcinbif_gpuDEVICE_CNTL_epf_DEFAULT__GFX09       0x2810
#define pcinbif_gpuDEVICE_CNTL_epvf_DEFAULT             0x0000
#define pcinbif_gpuDEVICE_CNTL_swds_DEFAULT__GFX09      0x2810
#define pcinbif_gpuDEVICE_ID_epf_DEFAULT__GFX09         0x0000
#define pcinbif_gpuDEVICE_ID_epvf_DEFAULT               0xFFFF
#define pcinbif_gpuDEVICE_ID_swds_DEFAULT__GFX09        0x0000
#define pcinbif_gpuDEVICE_STATUS2_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuDEVICE_STATUS2_epvf_DEFAULT          0x0000
#define pcinbif_gpuDEVICE_STATUS2_swds_DEFAULT__GFX09   0x0000
#define pcinbif_gpuDEVICE_STATUS_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuDEVICE_STATUS_epvf_DEFAULT           0x0000
#define pcinbif_gpuDEVICE_STATUS_swds_DEFAULT__GFX09    0x0000
#define pcinbif_gpuHEADER_epf_DEFAULT__GFX09            0x0000
#define pcinbif_gpuHEADER_epvf_DEFAULT                  0x0000
#define pcinbif_gpuHEADER_swds_DEFAULT__GFX09           0x0001
#define pcinbif_gpuINTERRUPT_LINE_epf_DEFAULT__GFX09    0x00FF
#define pcinbif_gpuINTERRUPT_LINE_epvf_DEFAULT          0x0000
#define pcinbif_gpuINTERRUPT_LINE_swds_DEFAULT__GFX09   0x00FF
#define pcinbif_gpuINTERRUPT_PIN_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuINTERRUPT_PIN_epvf_DEFAULT           0x0000
#define pcinbif_gpuINTERRUPT_PIN_swds_DEFAULT__GFX09    0x0001
#define pcinbif_gpuIO_BASE_LIMIT_HI_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuIO_BASE_LIMIT_swds_DEFAULT__GFX09    0x0101
#define pcinbif_gpuIRQ_BRIDGE_CNTL_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuLATENCY_epf_DEFAULT__GFX09           0x0000
#define pcinbif_gpuLATENCY_epvf_DEFAULT                 0x0000
#define pcinbif_gpuLATENCY_swds_DEFAULT__GFX09          0x0000
#define pcinbif_gpuLINK_CAP2_epf_DEFAULT__GFX09         0x000E
#define pcinbif_gpuLINK_CAP2_epvf_DEFAULT               0x000E
#define pcinbif_gpuLINK_CAP2_swds_DEFAULT__GFX09        0x000E
#define pcinbif_gpuLINK_CAP_epf_DEFAULT__GFX09          0x411C03
#define pcinbif_gpuLINK_CAP_swds_DEFAULT__GFX09         0x411C03
#define pcinbif_gpuLINK_CNTL2_epf_DEFAULT__GFX09        0x0003
#define pcinbif_gpuLINK_CNTL2_epvf_DEFAULT              0x0000
#define pcinbif_gpuLINK_CNTL2_swds_DEFAULT__GFX09       0x0003
#define pcinbif_gpuLINK_CNTL_epf_DEFAULT__GFX09         0x0000
#define pcinbif_gpuLINK_CNTL_epvf_DEFAULT               0x0000
#define pcinbif_gpuLINK_CNTL_swds_DEFAULT__GFX09        0x0000
#define pcinbif_gpuLINK_STATUS2_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuLINK_STATUS2_epvf_DEFAULT            0x0000
#define pcinbif_gpuLINK_STATUS2_swds_DEFAULT__GFX09     0x0000
#define pcinbif_gpuLINK_STATUS_epf_DEFAULT__GFX09       0x1001
#define pcinbif_gpuLINK_STATUS_epvf_DEFAULT             0x0000
#define pcinbif_gpuLINK_STATUS_swds_DEFAULT__GFX09      0x3001
#define pcinbif_gpuMAX_LATENCY_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuMEM_BASE_LIMIT_swds_DEFAULT__GFX09   0x0000
#define pcinbif_gpuMIN_GRANT_epf_DEFAULT__GFX09         0x0000
#define pcinbif_gpuMSIX_CAP_LIST_epf_DEFAULT__GFX09     0x0011
#define pcinbif_gpuMSIX_CAP_LIST_epvf_DEFAULT           0x0011
#define pcinbif_gpuMSIX_MSG_CNTL_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuMSIX_MSG_CNTL_epvf_DEFAULT           0x0000
#define pcinbif_gpuMSIX_PBA_epf_DEFAULT__GFX09          0x0000
#define pcinbif_gpuMSIX_PBA_epvf_DEFAULT                0x0000
#define pcinbif_gpuMSIX_TABLE_epf_DEFAULT__GFX09        0x0000
#define pcinbif_gpuMSIX_TABLE_epvf_DEFAULT              0x0000
#define pcinbif_gpuMSI_CAP_LIST_epf_DEFAULT__GFX09      0xC005
#define pcinbif_gpuMSI_CAP_LIST_epvf_DEFAULT            0xC005
#define pcinbif_gpuMSI_CAP_LIST_swds_DEFAULT__GFX09     0xC005
#define pcinbif_gpuMSI_MASK_64_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuMSI_MASK_64_epvf_DEFAULT             0x0000
#define pcinbif_gpuMSI_MASK_epf_DEFAULT__GFX09          0x0000
#define pcinbif_gpuMSI_MASK_epvf_DEFAULT                0x0000
#define pcinbif_gpuMSI_MSG_ADDR_HI_epf_DEFAULT__GFX09   0x0000
#define pcinbif_gpuMSI_MSG_ADDR_HI_epvf_DEFAULT         0x0000
#define pcinbif_gpuMSI_MSG_ADDR_HI_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuMSI_MSG_ADDR_LO_epf_DEFAULT__GFX09   0x0000
#define pcinbif_gpuMSI_MSG_ADDR_LO_epvf_DEFAULT         0x0000
#define pcinbif_gpuMSI_MSG_ADDR_LO_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuMSI_MSG_CNTL_epf_DEFAULT__GFX09      0x0080
#define pcinbif_gpuMSI_MSG_CNTL_swds_DEFAULT__GFX09     0x0080
#define pcinbif_gpuMSI_MSG_DATA_64_epf_DEFAULT__GFX09   0x0000
#define pcinbif_gpuMSI_MSG_DATA_64_epvf_DEFAULT         0x0000
#define pcinbif_gpuMSI_MSG_DATA_64_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuMSI_MSG_DATA_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuMSI_MSG_DATA_epvf_DEFAULT            0x0000
#define pcinbif_gpuMSI_MSG_DATA_swds_DEFAULT__GFX09     0x0000
#define pcinbif_gpuMSI_PENDING_64_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuMSI_PENDING_64_epvf_DEFAULT          0x0000
#define pcinbif_gpuMSI_PENDING_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuMSI_PENDING_epvf_DEFAULT             0x0000
#define pcinbif_gpuPCIE_ACS_CAP_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_ACS_CAP_swds_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_ACS_CNTL_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_ACS_CNTL_swds_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_ACS_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2B01000D
#define pcinbif_gpuPCIE_ACS_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x2F01000D
#define pcinbif_gpuPCIE_ADV_ERR_CAP_CNTL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_ADV_ERR_CAP_CNTL_epvf_DEFAULT   0x0000
#define pcinbif_gpuPCIE_ADV_ERR_CAP_CNTL_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x20020001
#define pcinbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_DEFAULT 0x20020001
#define pcinbif_gpuPCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x20020001
#define pcinbif_gpuPCIE_ARI_CAP_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_ARI_CAP_epvf_DEFAULT            0x0000
#define pcinbif_gpuPCIE_ARI_CNTL_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_ARI_CNTL_epvf_DEFAULT           0x0000
#define pcinbif_gpuPCIE_ARI_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x3301000E
#define pcinbif_gpuPCIE_ARI_ENH_CAP_LIST_epvf_DEFAULT   0x3301000E
#define pcinbif_gpuPCIE_ATS_CAP_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_ATS_CAP_epvf_DEFAULT            0x0000
#define pcinbif_gpuPCIE_ATS_CNTL_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_ATS_CNTL_epvf_DEFAULT           0x0000
#define pcinbif_gpuPCIE_ATS_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2C01000F
#define pcinbif_gpuPCIE_ATS_ENH_CAP_LIST_epvf_DEFAULT   0x2C01000F
#define pcinbif_gpuPCIE_BAR1_CAP_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_BAR1_CNTL_epf_DEFAULT__GFX09    0x0020
#define pcinbif_gpuPCIE_BAR2_CAP_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_BAR2_CNTL_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_BAR3_CAP_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_BAR3_CNTL_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_BAR4_CAP_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_BAR4_CNTL_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_BAR5_CAP_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_BAR5_CNTL_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_BAR6_CAP_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_BAR6_CNTL_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_BAR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x24010015
#define pcinbif_gpuPCIE_CAP_LIST_epf_DEFAULT__GFX09     0xA010
#define pcinbif_gpuPCIE_CAP_LIST_epvf_DEFAULT           0xA010
#define pcinbif_gpuPCIE_CAP_LIST_swds_DEFAULT__GFX09    0xA010
#define pcinbif_gpuPCIE_CAP_epf_DEFAULT__GFX09          0x0002
#define pcinbif_gpuPCIE_CAP_epvf_DEFAULT                0x0002
#define pcinbif_gpuPCIE_CAP_swds_DEFAULT__GFX09         0x0062
#define pcinbif_gpuPCIE_CORR_ERR_MASK_epf_DEFAULT__GFX09 0x2000
#define pcinbif_gpuPCIE_CORR_ERR_MASK_epvf_DEFAULT      0x0000
#define pcinbif_gpuPCIE_CORR_ERR_MASK_swds_DEFAULT__GFX09 0x2000
#define pcinbif_gpuPCIE_CORR_ERR_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_CORR_ERR_STATUS_epvf_DEFAULT    0x0000
#define pcinbif_gpuPCIE_CORR_ERR_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DEV_SERIAL_NUM_DW1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DEV_SERIAL_NUM_DW1_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DEV_SERIAL_NUM_DW2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DEV_SERIAL_NUM_DW2_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x15010003
#define pcinbif_gpuPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x15010003
#define pcinbif_gpuPCIE_DPA_CAP_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_DPA_CNTL_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_DPA_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x27010016
#define pcinbif_gpuPCIE_DPA_LATENCY_INDICATOR_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_STATUS_epf_DEFAULT__GFX09   0x0100
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_HDR_LOG0_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_HDR_LOG0_epvf_DEFAULT           0x0000
#define pcinbif_gpuPCIE_HDR_LOG0_swds_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_HDR_LOG1_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_HDR_LOG1_epvf_DEFAULT           0x0000
#define pcinbif_gpuPCIE_HDR_LOG1_swds_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_HDR_LOG2_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_HDR_LOG2_epvf_DEFAULT           0x0000
#define pcinbif_gpuPCIE_HDR_LOG2_swds_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_HDR_LOG3_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_HDR_LOG3_epvf_DEFAULT           0x0000
#define pcinbif_gpuPCIE_HDR_LOG3_swds_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_LANE_0_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_0_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_10_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_10_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_11_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_11_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_12_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_12_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_13_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_13_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_14_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_14_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_15_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_15_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_1_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_1_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_2_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_2_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_3_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_3_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_4_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_4_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_5_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_5_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_6_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_6_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_7_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_7_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_8_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_8_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_9_EQUALIZATION_CNTL_epf_DEFAULT__GFX09 0x7F00
#define pcinbif_gpuPCIE_LANE_9_EQUALIZATION_CNTL_swds_DEFAULT__GFX09 0x7F0F
#define pcinbif_gpuPCIE_LANE_ERROR_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_LANE_ERROR_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_LINK_CNTL3_epf_DEFAULT__GFX09   0x0000
#define pcinbif_gpuPCIE_LINK_CNTL3_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuPCIE_LTR_CAP_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_LTR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x32810018
#define pcinbif_gpuPCIE_MC_ADDR0_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_MC_ADDR1_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuPCIE_MC_BLOCK_ALL0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_MC_BLOCK_ALL1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_MC_BLOCK_UNTRANSLATED_0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_MC_BLOCK_UNTRANSLATED_1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_MC_CAP_epf_DEFAULT__GFX09       0x003F
#define pcinbif_gpuPCIE_MC_CNTL_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_MC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x32010012
#define pcinbif_gpuPCIE_MC_RCV0_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_MC_RCV1_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuPCIE_OUTSTAND_PAGE_REQ_ALLOC_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PAGE_REQ_CNTL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PAGE_REQ_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2D010013
#define pcinbif_gpuPCIE_PAGE_REQ_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PASID_CAP_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPCIE_PASID_CNTL_epf_DEFAULT__GFX09   0x0000
#define pcinbif_gpuPCIE_PASID_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2E01001B
#define pcinbif_gpuPCIE_PORT_VC_CAP_REG1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_CAP_REG1_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_CAP_REG2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_CAP_REG2_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_CNTL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_CNTL_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PORT_VC_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PWR_BUDGET_CAP_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PWR_BUDGET_DATA_SELECT_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PWR_BUDGET_DATA_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_PWR_BUDGET_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x25010004
#define pcinbif_gpuPCIE_SECONDARY_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2A010019
#define pcinbif_gpuPCIE_SECONDARY_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x2A010019
#define pcinbif_gpuPCIE_SRIOV_CAP_epf_DEFAULT__GFX09    0x0002
#define pcinbif_gpuPCIE_SRIOV_CONTROL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x40010010
#define pcinbif_gpuPCIE_SRIOV_FIRST_VF_OFFSET_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_FUNC_DEP_LINK_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_INITIAL_VFS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_NUM_VFS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_SYSTEM_PAGE_SIZE_epf_DEFAULT__GFX09 0x0001
#define pcinbif_gpuPCIE_SRIOV_TOTAL_VFS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_BASE_ADDR_0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_BASE_ADDR_1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_BASE_ADDR_2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_BASE_ADDR_3_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_BASE_ADDR_4_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_BASE_ADDR_5_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_DEVICE_ID_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_SRIOV_VF_STRIDE_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG0_epvf_DEFAULT    0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG0_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG1_epvf_DEFAULT    0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG1_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG2_epvf_DEFAULT    0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG2_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG3_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG3_epvf_DEFAULT    0x0000
#define pcinbif_gpuPCIE_TLP_PREFIX_LOG3_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TPH_REQR_CAP_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TPH_REQR_CNTL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_TPH_REQR_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x2F010017
#define pcinbif_gpuPCIE_UNCORR_ERR_MASK_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_UNCORR_ERR_MASK_epvf_DEFAULT    0x0000
#define pcinbif_gpuPCIE_UNCORR_ERR_MASK_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_UNCORR_ERR_SEVERITY_epf_DEFAULT__GFX09 0x462030
#define pcinbif_gpuPCIE_UNCORR_ERR_SEVERITY_epvf_DEFAULT 0x0000
#define pcinbif_gpuPCIE_UNCORR_ERR_SEVERITY_swds_DEFAULT__GFX09 0x462030
#define pcinbif_gpuPCIE_UNCORR_ERR_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_UNCORR_ERR_STATUS_epvf_DEFAULT  0x0000
#define pcinbif_gpuPCIE_UNCORR_ERR_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC0_RESOURCE_CAP_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC0_RESOURCE_CAP_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC0_RESOURCE_CNTL_epf_DEFAULT__GFX09 0x800000FF
#define pcinbif_gpuPCIE_VC0_RESOURCE_CNTL_swds_DEFAULT__GFX09 0x800000FF
#define pcinbif_gpuPCIE_VC0_RESOURCE_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC0_RESOURCE_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC1_RESOURCE_CAP_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC1_RESOURCE_CAP_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC1_RESOURCE_CNTL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC1_RESOURCE_CNTL_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC1_RESOURCE_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC1_RESOURCE_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x14010002
#define pcinbif_gpuPCIE_VC_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x14010002
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC1_epvf_DEFAULT   0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC1_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC2_epvf_DEFAULT   0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC2_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf_DEFAULT__GFX09 0x1000B
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf_DEFAULT__GFX09 0x1101000B
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_DEFAULT 0x1101000B
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds_DEFAULT__GFX09 0x1101000B
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf_DEFAULT__GFX09 0xF020002
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_epf_DEFAULT__GFX09 0x1010001
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_epvf_DEFAULT 0x1010001
#define pcinbif_gpuPCIE_VENDOR_SPECIFIC_HDR_swds_DEFAULT__GFX09 0x1010001
#define pcinbif_gpuPMI_CAP_LIST_epf_DEFAULT__GFX09      0x0001
#define pcinbif_gpuPMI_CAP_LIST_swds_DEFAULT__GFX09     0x5801
#define pcinbif_gpuPMI_CAP_epf_DEFAULT__GFX09           0x0003
#define pcinbif_gpuPMI_CAP_swds_DEFAULT__GFX09          0x0003
#define pcinbif_gpuPMI_STATUS_CNTL_epf_DEFAULT__GFX09   0x0000
#define pcinbif_gpuPMI_STATUS_CNTL_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuPREF_BASE_LIMIT_swds_DEFAULT__GFX09  0x10001
#define pcinbif_gpuPREF_BASE_UPPER_swds_DEFAULT__GFX09  0x0000
#define pcinbif_gpuPREF_LIMIT_UPPER_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuPROG_INTERFACE_epf_DEFAULT__GFX09    0x0000
#define pcinbif_gpuPROG_INTERFACE_epvf_DEFAULT          0x0000
#define pcinbif_gpuPROG_INTERFACE_swds_DEFAULT__GFX09   0x0000
#define pcinbif_gpuREVISION_ID_epf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuREVISION_ID_epvf_DEFAULT             0x0000
#define pcinbif_gpuREVISION_ID_swds_DEFAULT__GFX09      0x0000
#define pcinbif_gpuROM_BASE_ADDR_epf_DEFAULT__GFX09     0x0000
#define pcinbif_gpuROM_BASE_ADDR_epvf_DEFAULT           0x0000
#define pcinbif_gpuSECONDARY_STATUS_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuSHADOW_BASE_ADDR_1_DEFAULT           0x0000
#define pcinbif_gpuSHADOW_BASE_ADDR_2_DEFAULT           0x0000
#define pcinbif_gpuSHADOW_COMMAND_DEFAULT               0x0000
#define pcinbif_gpuSHADOW_IO_BASE_LIMIT_DEFAULT         0x0000
#define pcinbif_gpuSHADOW_IO_BASE_LIMIT_HI_DEFAULT      0x0000
#define pcinbif_gpuSHADOW_IRQ_BRIDGE_CNTL_DEFAULT       0x0000
#define pcinbif_gpuSHADOW_MEM_BASE_LIMIT_DEFAULT        0x0000
#define pcinbif_gpuSHADOW_PREF_BASE_LIMIT_DEFAULT       0x10001
#define pcinbif_gpuSHADOW_PREF_BASE_UPPER_DEFAULT       0x0000
#define pcinbif_gpuSHADOW_PREF_LIMIT_UPPER_DEFAULT      0x0000
#define pcinbif_gpuSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x0000
#define pcinbif_gpuSLOT_CAP2_epf_DEFAULT__GFX09         0x0000
#define pcinbif_gpuSLOT_CAP2_epvf_DEFAULT               0x0000
#define pcinbif_gpuSLOT_CAP2_swds_DEFAULT__GFX09        0x0000
#define pcinbif_gpuSLOT_CAP_swds_DEFAULT__GFX09         0x0000
#define pcinbif_gpuSLOT_CNTL2_epf_DEFAULT__GFX09        0x0000
#define pcinbif_gpuSLOT_CNTL2_epvf_DEFAULT              0x0000
#define pcinbif_gpuSLOT_CNTL2_swds_DEFAULT__GFX09       0x0000
#define pcinbif_gpuSLOT_CNTL_swds_DEFAULT__GFX09        0x0000
#define pcinbif_gpuSLOT_STATUS2_epf_DEFAULT__GFX09      0x0000
#define pcinbif_gpuSLOT_STATUS2_epvf_DEFAULT            0x0000
#define pcinbif_gpuSLOT_STATUS2_swds_DEFAULT__GFX09     0x0000
#define pcinbif_gpuSLOT_STATUS_swds_DEFAULT__GFX09      0x0040
#define pcinbif_gpuSSID_CAP_LIST_swds_DEFAULT__GFX09    0x000D
#define pcinbif_gpuSSID_CAP_swds_DEFAULT__GFX09         0x0000
#define pcinbif_gpuSTATUS_epf_DEFAULT__GFX09            0x0010
#define pcinbif_gpuSTATUS_epvf_DEFAULT                  0x0010
#define pcinbif_gpuSTATUS_swds_DEFAULT__GFX09           0x0010
#define pcinbif_gpuSUB_BUS_NUMBER_LATENCY_swds_DEFAULT__GFX09 0x0000
#define pcinbif_gpuSUB_CLASS_epf_DEFAULT__GFX09         0x0000
#define pcinbif_gpuSUB_CLASS_epvf_DEFAULT               0x0000
#define pcinbif_gpuSUB_CLASS_swds_DEFAULT__GFX09        0x0000
#define pcinbif_gpuVENDOR_CAP_LIST_epf_DEFAULT__GFX09   0x85009
#define pcinbif_gpuVENDOR_ID_epf_DEFAULT__GFX09         0x0000
#define pcinbif_gpuVENDOR_ID_epvf_DEFAULT               0xFFFF
#define pcinbif_gpuVENDOR_ID_swds_DEFAULT__GFX09        0x0000
#define cfgnbif_gpuADAPTER_ID_epvf_DEFAULT__GFX09       0x0000
#define cfgnbif_gpuCAP_PTR_epvf_DEFAULT__GFX09          0x0000
#define cfgnbif_gpuDEVICE_CAP_epvf_DEFAULT__GFX09       0x10000020
#define cfgnbif_gpuLINK_CAP_epvf_DEFAULT__GFX09         0x411C03
#define cfgnbif_gpuMSI_MSG_CNTL_epvf_DEFAULT__GFX09     0x0080
#define mmATC_ATS_CNTL_DEFAULT__GFX09                   0x9A0800
#define mmATHUB_MISC_CNTL_DEFAULT__GFX09                0x40200
#define mmCB_COLOR0_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR0_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR0_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR0_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR1_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR1_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR1_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR1_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR2_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR2_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR2_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR2_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR3_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR3_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR3_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR3_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR4_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR4_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR4_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR4_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR5_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR5_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR5_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR5_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR6_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR6_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR6_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR6_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_COLOR7_ATTRIB_DEFAULT__GFX09               0xCDCDCDCD
#define mmCB_COLOR7_DCC_CONTROL_DEFAULT__GFX09          0x1CDCD
#define mmCB_COLOR7_INFO_DEFAULT__GFX09                 0xC05CD4D
#define mmCB_COLOR7_VIEW_DEFAULT__GFX09                 0xDCDC5CD
#define mmCB_DCC_CONFIG_DEFAULT__GFX09                  0x4000000
#define mmCB_DCC_CONTROL_DEFAULT__GFX09                 0x004D
#define mmCB_HW_CONTROL_2_DEFAULT__GFX09                0x0000
#define mmCB_HW_CONTROL_3_DEFAULT__GFX09                0x0000
#define mmCB_HW_CONTROL_DEFAULT__GFX09                  0x14107
#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT__GFX09      0x0000
#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT__GFX09     0x4C4D
#define mmCOMPUTE_MISC_RESERVED_DEFAULT__GFX09          0x0002
#define mmCOMPUTE_PGM_RSRC1_DEFAULT__GFX09              0x5CDCDCD
#define mmCOMPUTE_PGM_RSRC2_DEFAULT__GFX09              0xCDCDCDCD
#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0x11000401
#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0x11000401
#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0x11000401
#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0x11000401
#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0x11000401
#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0x11000401
#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0x11000401
#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0x11000401
#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0x11000401
#define mmCP_APPEND_ADDR_HI_DEFAULT__GFX09              0xC001CDCD
#define mmCP_CEQ1_AVAIL_DEFAULT__GFX09                  0x5CD05CD
#define mmCP_CEQ2_AVAIL_DEFAULT__GFX09                  0x05CD
#define mmCP_CE_ROQ_IB1_STAT_DEFAULT__GFX09             0x1CD01CD
#define mmCP_CE_ROQ_IB2_STAT_DEFAULT__GFX09             0x1CD01CD
#define mmCP_CE_ROQ_RB_STAT_DEFAULT__GFX09              0x1CD01CD
#define mmCP_CPC_IC_BASE_CNTL_DEFAULT__GFX09            0x0000
#define mmCP_CPC_STATUS_DEFAULT__GFX09                  0xC0004CCD
#define mmCP_CPF_BUSY_STAT_DEFAULT__GFX09               0xCDCDC9CD
#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT__GFX09         0x0004
#define mmCP_CPF_STATUS_DEFAULT__GFX09                  0xCC01CDC1
#define mmCP_DMA_CNTL_DEFAULT__GFX09                    0x80030
#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT__GFX09         0x1C04D
#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT__GFX09         0x0000
#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT__GFX09         0x0000
#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT__GFX09          0x0000
#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT__GFX09          0x0000
#define mmCP_ME_MC_RADDR_HI_DEFAULT__GFX09              0x40CDCD
#define mmCP_ME_MC_WADDR_HI_DEFAULT__GFX09              0x40CDCD
#define mmCP_RB0_ACTIVE_DEFAULT__GFX09                  0x0001
#define mmCP_RB0_CNTL_DEFAULT__GFX09                    0x400000
#define mmCP_RB1_CNTL_DEFAULT__GFX09                    0x400000
#define mmCP_RB2_CNTL_DEFAULT__GFX09                    0x400000
#define mmCP_RB_ACTIVE_DEFAULT__GFX09                   0x0001
#define mmCP_RB_CNTL_DEFAULT__GFX09                     0x400000
#define mmCP_ROQ1_THRESHOLDS_DEFAULT__GFX09             0x30101010
#define mmCP_ROQ2_AVAIL_DEFAULT__GFX09                  0x05CD
#define mmCP_ROQ2_THRESHOLDS_DEFAULT__GFX09             0x40403030
#define mmCP_ROQ_AVAIL_DEFAULT__GFX09                   0x5CD05CD
#define mmCP_ROQ_IB1_STAT_DEFAULT__GFX09                0x1CD01CD
#define mmCP_ROQ_IB2_STAT_DEFAULT__GFX09                0x1CD01CD
#define mmCP_ROQ_RB_STAT_DEFAULT__GFX09                 0x1CD01CD
#define mmCP_SD_CNTL_DEFAULT__GFX09                     0x001F
#define mmCP_STALLED_STAT2_DEFAULT__GFX09               0xCDCDCD05
#define mmCP_STAT_DEFAULT__GFX09                        0xCDCDCC00
#define mmDB_DEBUG2_DEFAULT__GFX09                      0x0000
#define mmDB_DEBUG3_DEFAULT__GFX09                      0x0000
#define mmDB_DEBUG4_DEFAULT__GFX09                      0x0000
#define mmDB_DEPTH_SIZE_DEFAULT__GFX09                  0xDCD0DCD
#define mmDB_DEPTH_VIEW_DEFAULT__GFX09                  0xDCDC5CD
#define mmDB_DFSM_CONFIG_DEFAULT__GFX09                 0x7F00
#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT__GFX09           0x03FF
#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT__GFX09        0xFA00C8
#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT__GFX09        0x5DC03E8
#define mmDB_EQAA_DEFAULT__GFX09                        0xD0D4545
#define mmDB_HTILE_SURFACE_DEFAULT__GFX09               0xDCDCC
#define mmDB_RENDER_OVERRIDE2_DEFAULT__GFX09            0xCDCDCD
#define mmDB_SHADER_CONTROL_DEFAULT__GFX09              0x41CDC5
#define mmDB_STENCIL_INFO_DEFAULT__GFX09                0x4800C001
#define mmDB_WATERMARKS_DEFAULT__GFX09                  0x1020204
#define mmDB_Z_INFO_DEFAULT__GFX09                      0xCD8DC1CC
#define mmGB_ADDR_CONFIG_DEFAULT__GFX09                 0x2A110012
#define mmGB_ADDR_CONFIG_READ_DEFAULT__GFX09            0x2A110012
#define mmGB_BACKEND_MAP_DEFAULT__GFX09                 0x76541032
#define mmGB_MACROTILE_MODE0_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE10_DEFAULT__GFX09            0x0000
#define mmGB_MACROTILE_MODE11_DEFAULT__GFX09            0x0000
#define mmGB_MACROTILE_MODE12_DEFAULT__GFX09            0x0000
#define mmGB_MACROTILE_MODE13_DEFAULT__GFX09            0x0000
#define mmGB_MACROTILE_MODE1_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE2_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE3_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE4_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE5_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE6_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE8_DEFAULT__GFX09             0x0000
#define mmGB_MACROTILE_MODE9_DEFAULT__GFX09             0x0000
#define mmGC_CAC_CTRL_1_DEFAULT__GFX09                  0x1000000
#define mmGC_EDC_CTRL_DEFAULT__GFX09                    0x0000
#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT__GFX09        0x07FF
#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT__GFX09       0xDCDCD
#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT__GFX09        0xCDCDCD
#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT__GFX09        0xCDCDCD
#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT__GFX09        0xCDCDCD
#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT__GFX09        0xCDCDCD
#define mmGRBM_STATUS2_DEFAULT__GFX09                   0xC50DCDCD
#define mmGRBM_STATUS_DEFAULT__GFX09                    0xC5CDC18D
#define mmGRBM_STATUS_SE0_DEFAULT__GFX09                0xCDC00004
#define mmGRBM_STATUS_SE1_DEFAULT__GFX09                0xCDC00004
#define mmGRBM_STATUS_SE2_DEFAULT__GFX09                0xCDC00004
#define mmGRBM_STATUS_SE3_DEFAULT__GFX09                0xCDC00004
#define mmIA_MULTI_VGT_PARAM_DEFAULT__GFX09             0x6000FF
#define mmIH_CNTL2_DEFAULT__GFX09                       0x00FF
#define mmIH_MMHUB_CNTL_DEFAULT__GFX09                  0x0001
#define mmIH_STATUS_DEFAULT__GFX09                      0x40847
#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT__GFX09         0x0000
#define mmPA_CL_CNTL_STATUS_DEFAULT__GFX09              0x0005
#define mmPA_CL_ENHANCE_DEFAULT__GFX09                  0x0007
#define mmPA_SC_BINNER_CNTL_0_DEFAULT__GFX09            0xDCDCDCD
#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT__GFX09      0x8A000008
#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT__GFX09      0x9118AAA8
#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT__GFX09      0x82400025
#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT__GFX09 0x1CDCDCD
#define mmPA_SC_ENHANCE_1_DEFAULT__GFX09                0x40000
#define mmPA_SC_ENHANCE_DEFAULT__GFX09                  0x0001
#define mmPA_SC_NGG_MODE_CNTL_DEFAULT__GFX09            0x05CD
#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT__GFX09     0xDCDCD
#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT__GFX09      0xCDCDCD
#define mmPA_SC_RASTER_CONFIG_1_DEFAULT__GFX09          0x00CD
#define mmPA_SC_RASTER_CONFIG_DEFAULT__GFX09            0xCD0DCDCD
#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT__GFX09   0x0145
#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT__GFX09     0xDCDCD
#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT__GFX09      0xCDCDCD
#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT__GFX09     0xDCDCD
#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT__GFX09      0xCDCDCD
#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT__GFX09      0xC001CD
#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT__GFX09      0xC001CD
#define mmPA_SU_SC_MODE_CNTL_DEFAULT__GFX09             0xC90DCD
#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT__GFX09   0x000D
#define mmRAS_SPI_SIGNATURE0_DEFAULT__GFX09             0x0000
#define mmRAS_SPI_SIGNATURE1_DEFAULT__GFX09             0x0000
#define mmRLC_CLK_CNTL_DEFAULT__GFX09                   0x0003
#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT__GFX09        0x0000
#define mmRLC_GPM_STAT_DEFAULT__GFX09                   0x100016
#define mmRLC_GPM_THREAD_RESET_DEFAULT__GFX09           0x000F
#define mmRLC_GPM_TIMER_INT_0_DEFAULT__GFX09            0x0000
#define mmRLC_GPM_TIMER_INT_1_DEFAULT__GFX09            0x0000
#define mmRLC_GPM_TIMER_INT_2_DEFAULT__GFX09            0x0000
#define mmRLC_GPM_TIMER_INT_3_DEFAULT__GFX09            0x0000
#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT__GFX09        0x0000
#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT__GFX09 0xFFFF
#define mmRLC_GPU_IOV_VF_MASK_DEFAULT__GFX09            0x10001
#define mmRLC_LB_CNTL_DEFAULT__GFX09                    0x0010
#define mmRLC_PERFMON_CNTL_DEFAULT__GFX09               0x0400
#define mmRMI_GENERAL_CNTL1_DEFAULT__GFX09              0x1A03
#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT__GFX09       0x340D0
#define mmRMI_SPARE_DEFAULT__GFX09                      0x0001
#define mmRPB_SDPPORT_CNTL_DEFAULT__GFX09               0xFD14814
#define mmRPB_TAG_CONF_DEFAULT__GFX09                   0x204020
#define mmSDMA0_CHICKEN_BITS_DEFAULT__GFX09             0x831F07
#define mmSDMA0_CLK_CTRL_DEFAULT__GFX09                 0xFF000100
#define mmSDMA0_CNTL_DEFAULT__GFX09                     0x0002
#define mmSDMA0_CRD_CNTL_DEFAULT__GFX09                 0x85C0
#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT__GFX09           0x100012
#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT__GFX09      0x100012
#define mmSDMA0_GFX_RB_CNTL_DEFAULT__GFX09              0x40000
#define mmSDMA0_PAGE_RB_CNTL_DEFAULT__GFX09             0x40000
#define mmSDMA0_POWER_CNTL_DEFAULT__GFX09               0x3C000
#define mmSDMA0_PUB_REG_TYPE0_DEFAULT__GFX09            0x3C000000
#define mmSDMA0_PUB_REG_TYPE2_DEFAULT__GFX09            0xFC6E880
#define mmSDMA0_PUB_REG_TYPE3_DEFAULT__GFX09            0x0000
#define mmSDMA0_RD_BURST_CNTL_DEFAULT__GFX09            0x0003
#define mmSDMA0_RLC0_RB_CNTL_DEFAULT__GFX09             0x40000
#define mmSDMA0_RLC1_RB_CNTL_DEFAULT__GFX09             0x40000
#define mmSDMA0_STATUS3_REG_DEFAULT__GFX09              0x100000
#define mmSDMA0_UTCL1_CNTL_DEFAULT__GFX09               0xD0003019
#define mmSDMA0_UTCL1_INV0_DEFAULT__GFX09               0x0600
#define mmSDMA0_UTCL1_PAGE_DEFAULT__GFX09               0x03E0
#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT__GFX09          0x201001FF
#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT__GFX09            0x10001
#define mmSDMA0_UTCL1_WATERMK_DEFAULT__GFX09            0xFFFBE1FE
#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT__GFX09          0x503001FF
#define mmSDMA0_VERSION_DEFAULT__GFX09                  0x0400
#define mmSDMA0_VM_CTX_CNTL_DEFAULT__GFX09              0x0000
#define mmSDMA1_CHICKEN_BITS_DEFAULT__GFX09             0x831F07
#define mmSDMA1_CLK_CTRL_DEFAULT__GFX09                 0xFF000100
#define mmSDMA1_CNTL_DEFAULT__GFX09                     0x0002
#define mmSDMA1_CRD_CNTL_DEFAULT__GFX09                 0x85C0
#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT__GFX09           0x100012
#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT__GFX09      0x100012
#define mmSDMA1_GFX_RB_CNTL_DEFAULT__GFX09              0x40000
#define mmSDMA1_PAGE_RB_CNTL_DEFAULT__GFX09             0x40000
#define mmSDMA1_POWER_CNTL_DEFAULT__GFX09               0x3C000
#define mmSDMA1_PUB_REG_TYPE0_DEFAULT__GFX09            0x3C000000
#define mmSDMA1_PUB_REG_TYPE2_DEFAULT__GFX09            0xFC6E880
#define mmSDMA1_PUB_REG_TYPE3_DEFAULT__GFX09            0x0000
#define mmSDMA1_RD_BURST_CNTL_DEFAULT__GFX09            0x0003
#define mmSDMA1_RLC0_RB_CNTL_DEFAULT__GFX09             0x40000
#define mmSDMA1_RLC1_RB_CNTL_DEFAULT__GFX09             0x40000
#define mmSDMA1_STATUS3_REG_DEFAULT__GFX09              0x100000
#define mmSDMA1_UTCL1_CNTL_DEFAULT__GFX09               0xD0003019
#define mmSDMA1_UTCL1_INV0_DEFAULT__GFX09               0x0600
#define mmSDMA1_UTCL1_PAGE_DEFAULT__GFX09               0x03E0
#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT__GFX09          0x201001FF
#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT__GFX09            0x10001
#define mmSDMA1_UTCL1_WATERMK_DEFAULT__GFX09            0xFFFBE1FE
#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT__GFX09          0x503001FF
#define mmSDMA1_VERSION_DEFAULT__GFX09                  0x0400
#define mmSDMA1_VM_CTX_CNTL_DEFAULT__GFX09              0x0000
#define mmSEM_CHICKEN_BITS_DEFAULT__GFX09               0x84AD6
#define mmSEM_MMHUB_CNTL_DEFAULT__GFX09                 0x0000
#define mmSEM_RESP_ACP_DEFAULT__GFX09                   0x4870C
#define mmSEM_RESP_GC_DEFAULT__GFX09                    0x4858C
#define mmSEM_RESP_SDMA0_DEFAULT__GFX09                 0x4950C
#define mmSEM_RESP_SDMA1_DEFAULT__GFX09                 0x4958C
#define mmSEM_RESP_UVD_DEFAULT__GFX09                   0x4860C
#define mmSEM_RESP_VCE_0_DEFAULT__GFX09                 0x4900C
#define mmSEM_RESP_VCE_1_DEFAULT__GFX09                 0x4908C
#define mmSPI_CONFIG_CNTL_1_DEFAULT__GFX09              0x1000106
#define mmSPI_CONFIG_CNTL_DEFAULT__GFX09                0x62C688
#define mmSPI_DEBUG_BUSY_DEFAULT__GFX09                 0xDCDCD
#define mmSPI_EDC_CNT_DEFAULT__GFX09                    0x0000
#define mmSPI_GDS_CREDITS_DEFAULT__GFX09                0x1080
#define mmSPI_LB_DATA_WAVES_DEFAULT__GFX09              0xCDCDCDCD
#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT__GFX09        0x00FF
#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT__GFX09        0x00FF
#define mmSPI_PS_IN_CONTROL_DEFAULT__GFX09              0x41CD
#define mmSPI_PS_MAX_WAVE_ID_DEFAULT__GFX09             0x200017F
#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT__GFX09        0xC1CDCDCD
#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT__GFX09        0x48CDCDCD
#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT__GFX09        0x1CDCDCD
#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT__GFX09        0xC5CDCDCD
#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT__GFX09        0x9CDCDCD
#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT__GFX09        0x0800
#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT__GFX09        0x0000
#define mmSPI_SHADER_POS_FORMAT_DEFAULT__GFX09          0xCDCD
#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT__GFX09     0x8000400
#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT__GFX09 0x200040
#define mmSPI_VS_OUT_CONFIG_DEFAULT__GFX09              0x004C
#define mmSQC_CONFIG_DEFAULT__GFX09                     0x10A2000
#define mmSQ_CMD_DEFAULT__GFX09                         0xC50D0DC5
#define mmSQ_FIFO_SIZES_DEFAULT__GFX09                  0x0F01
#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT__GFX09        0xF0FF000
#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT__GFX09        0xF0FF000
#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT__GFX09        0xF0FF000
#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT__GFX09        0xF0FF000
#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT__GFX09        0xF0FF000
#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT__GFX09        0xF0FF000
#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT__GFX09         0xF0FF000
#define mmSQ_PERFCOUNTER_CTRL_DEFAULT__GFX09            0x0000
#define mmSQ_THREAD_TRACE_MASK_DEFAULT__GFX09           0xCF80
#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT__GFX09     0xFFFFFF
#define mmSQ_THREAD_TRACE_WPTR_DEFAULT__GFX09           0xDCDCDCD
#define mmSQ_WREXEC_EXEC_HI_DEFAULT__GFX09              0xCC00CDCD
#define mmTA_CNTL_AUX_DEFAULT__GFX09                    0x0000
#define mmTA_CNTL_DEFAULT__GFX09                        0x8004D850
#define mmTA_PERFCOUNTER1_SELECT_DEFAULT__GFX09         0x1CCCD
#define mmTCP_CNTL_DEFAULT__GFX09                       0x2F9C0000
#define mmTCP_CREDIT_DEFAULT__GFX09                     0x804001C0
#define mmTCP_STATUS_DEFAULT__GFX09                     0x01CD
#define mmTD_PERFCOUNTER1_SELECT_DEFAULT__GFX09         0x1CCCD
#define mmVGT_DMA_CONTROL_DEFAULT__GFX09                0x4000FF
#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT__GFX09        0x40180
#define mmVGT_DMA_INDEX_TYPE_DEFAULT__GFX09             0x054D
#define mmVGT_FIFO_DEPTHS_DEFAULT__GFX09                0x80DCDC0
#define mmVGT_INDEX_TYPE_DEFAULT__GFX09                 0x0101
#define mmVGT_SHADER_STAGES_EN_DEFAULT__GFX09           0xDCCCD
#define mmVGT_STRMOUT_DELAY_DEFAULT__GFX09              0x92420
#define mmVGT_TF_PARAM_DEFAULT__GFX09                   0x4C1CD
#define mmVGT_TF_RING_SIZE_DEFAULT__GFX09               0x2000
#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT__GFX09          0x0000
#define mmXPB_CLG_MM_MATCH_DEFAULT__GFX09               0x3000000
#define mmnbif_gpuA2S_CNTL_CL0_DEFAULT__GFX09           0x280540
#define mmnbif_gpuA2S_CNTL_CL1_DEFAULT__GFX09           0x282540
#define mmnbif_gpuA2S_CNTL_SW0_DEFAULT__GFX09           0x8080005
#define mmnbif_gpuA2S_CNTL_SW1_DEFAULT__GFX09           0x8080205
#define mmnbif_gpuA2S_CNTL_SW2_DEFAULT__GFX09           0x8080200
#define mmnbif_gpuADAPTER_ID_epvf_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBASE_CLASS_swds_DEFAULT__GFX09        0x0000
#define mmnbif_gpuBIFC_MISC_CTRL1_DEFAULT__GFX09        0x10108C04
#define mmnbif_gpuBIF_RAS_LEAF0_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuBIF_RAS_LEAF1_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuBIF_RAS_LEAF2_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuCAP_PTR_epvf_DEFAULT__GFX09           0x0000
#define mmnbif_gpuDEVICE_CAP_epvf_DEFAULT__GFX09        0x10000020
#define mmnbif_gpuGDC_RAS_LEAF0_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuGDC_RAS_LEAF1_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuGDC_RAS_LEAF2_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuGDC_RAS_LEAF3_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuGDC_RAS_LEAF4_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuGDC_RAS_LEAF5_CTRL_DEFAULT__GFX09     0x0000
#define mmnbif_gpuINTERRUPT_PIN_swds_DEFAULT__GFX09     0x0001
#define mmnbif_gpuLINK_CAP_epvf_DEFAULT__GFX09          0x411C03
#define mmnbif_gpuLINK_CAP_swds_DEFAULT__GFX09          0x411C03
#define mmnbif_gpuMSI_MSG_CNTL_epvf_DEFAULT__GFX09      0x0080
#define mmnbif_gpuPMI_CAP_swds_DEFAULT__GFX09           0x0003
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP0_DEFAULT__GFX09   0x30000000
#define mmnbif_gpuRCC_DEV0_EPF0_STRAP8_DEFAULT__GFX09   0xC8C73002
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP0_DEFAULT__GFX09   0x0000
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP13_DEFAULT__GFX09  0x0000
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP2_DEFAULT__GFX09   0x0000
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP3_DEFAULT__GFX09   0x0000
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP4_DEFAULT__GFX09   0x0000
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP5_DEFAULT__GFX09   0x0000
#define mmnbif_gpuRCC_DEV0_EPF2_STRAP6_DEFAULT__GFX09   0x0000
#define mmnbif_gpuSHUB_HARD_RST_CTRL_DEFAULT__GFX09     0x001B
#define mmnbif_gpuSUB_CLASS_swds_DEFAULT__GFX09         0x0000
#define mmnbif_gpuVENDOR_ID_swds_DEFAULT__GFX09         0x0000
#define pcinbif_gpuADAPTER_ID_epvf_DEFAULT__GFX09       0x0000
#define pcinbif_gpuCAP_PTR_epvf_DEFAULT__GFX09          0x0000
#define pcinbif_gpuDEVICE_CAP_epvf_DEFAULT__GFX09       0x10000020
#define pcinbif_gpuLINK_CAP_epvf_DEFAULT__GFX09         0x411C03
#define pcinbif_gpuMSI_MSG_CNTL_epvf_DEFAULT__GFX09     0x0080
